EP1S40F1020C6 Altera, EP1S40F1020C6 Datasheet - Page 6

• Manufacturer Part Number: EP1S40F1020C6
• Description: IC STRATIX FPGA 40K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40F1020C6

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 773
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1425; EP1S40SF1020C6

Stratix Device Family Data Sheet
Section I–6
Chapter
4
November 2003, v2.2
April 2004, v3.0
Date/Version
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Updated
page
Updated Note 3 in
Table 4–125 on page
updated table.
Updated
Updated
Updated
Table 4–129 on page
Updated
Updated
Updated
Updated
page
Added Note 10 to
Moved
Updated
page
Deleted t
Waveform was added to
The minimum and maximum duty cycle values in Note 3 of
were moved to a new
Changes were made to values in SSTL-3 Class I and II rows in
Table
Note 1 was added to
Added t
Changed
Clock External I/O Timing Parameters” to “EP1S10 External I/O
Timing on Column Pins Using Fast Regional Clock Networks.”
Changed values in
Added t
Deleted -5 Speed Grade column in
to 4–123.
Fixed differential waveform in
Added
Added t
t
Values changed in the t
Values changed in the t
Values changed in the t
Added
The timing information is preliminary in
Table 4–111
Updated
CLKHL
4–92.
4–92.
4–100.
4–17.
rows in Table 4–46.
“Definition of I/O Skew”
Table 4–51
Table 4–127 on page 4–94
SU_R
ARESET
SU
XZ
Table 4–123 on page 4–85
Table 4–126 on page
Table 4–127 on page
Table 4–128 on page
Table 4–131
Table 4–110 on page
Table 4–123 on page
Table 4–124 on page
Table 4–131 on page 4–100
Tables 4–127
Table 4–55
and t
and t
and t
was separated into 3 tables:
row in
CO_C
ZX
SU_C
Table 4–129 on page
to
Table 4–123 on page
Tables
from
rows and made changes to values in t
“Internal Timing Parameters”
Table
title from “EP1S10 Column Pin Fast Regional
Tables 4–127
4–88: moved to correct order in chapter, and
4–96: updated table and added Note 10.
Table
and
rows in
through 4–129.
SU
M4KCLKHL
MRAMCLKHL
Figure
Changes Made
Figure
and t
Table 4–132 on page
4–46,
4–34.
4–9.
Figure
Table
4–92.
4–94.
4–95.
4–74.
4–85.
4–87. through
section.
H
4–4.
Stratix Device Handbook, Volume 1
4–6.
row in
4–48
rows in
row in
Tables 4–117
to correct order in the chapter.
to 4–132.
4–38.
through
4–1.
through
to 4–51, 4–128, and 4–131.
Table
Tables 4–55
4–96.
4–85.
Table
Table
Tables 4–111
Table 4–126 on
4–49.
Table 4–126 on
Table 4–132 on
4–50.
4–47.
4–100.
to
Altera Corporation
4–119
section.
through 4–96.
to 4–113.
and
Table 4–8
PRE
4–122
and