EP2S130F1508C3N Altera, EP2S130F1508C3N Datasheet - Page 61

• Manufacturer Part Number: EP2S130F1508C3N
• Description: IC STRATIX II FPGA 130K 1508FBGA
• Manufacturer: Altera
• Series: Stratix® IIr

Specifications of EP2S130F1508C3N

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 1126
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1508-FBGA
• Family Name: Stratix II
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 1126
• Frequency (max): 778.82MHz
• Process Technology: 90nm (CMOS)
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1508
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1869; EP2S130F1508C3N; Q2675539A

Figure 2–36. EP2S60, EP2S90, EP2S130 & EP2S180 Device I/O Clock Groups
Altera Corporation
May 2007
IO_CLKM[7:0]
IO_CLKO[7:0]
IO_CLKN[7:0]
IO_CLKP[7:0]
8
8
8
8
IO_CLKA[7:0]
8
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
IO_CLKL[7:0]
24 Clocks in the
24 Clocks in the
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable/disable)
8
Quadrant
Quadrant
IO_CLKB[7:0]
8
IO_CLKK[7:0]
8
IO_CLKC[7:0]
8
IO_CLKJ[7:0]
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
IO_CLKD[7:0]
Stratix II Device Handbook, Volume 1
8
IO_CLKI[7:0]
8
8
8
8
8
Stratix II Architecture
IO_CLKE[7:0]
IO_CLKF[7:0]
IO_CLKG[7:0]
IO_CLKH[7:0]
I/O Clock Regions
2–53