EP2SGX130GF1508I4 Altera, EP2SGX130GF1508I4 Datasheet - Page 206

• Manufacturer Part Number: EP2SGX130GF1508I4
• Description: IC STRATIX II GX 130K 1508-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX130GF1508I4

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 734
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1508-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 734
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1508
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2174

Operating Conditions
4–36
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
(11) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(12) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(13) The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification.
(14) The jitter numbers for (OIF) CEI are compliant to the OIF-CEI-02.0 Specification.
(15) The jitter numbers for CPRI are compliant to the CPRI Specification V2.1.
(16) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications.
(17) The Fibre Channel transmitter jitter generation numbers are compliant to the specification at β
(18) The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at β
PCI-E
(OIF) CEI
PHY
GIGE
XAUI
Table 4–19. Stratix II GX Transceiver Block AC Specification
Table 4–20. Recommended Input Clock Jitter (Part 1 of 2)
Description
Mode
Dedicated REFCLK pins were used to drive the input reference clocks.
Jitter numbers specified are valid for the stated conditions only.
Refer to the protocol characterization documents for detailed information.
HiGig configuration is available in a -3 speed grade only. For more information, refer to the
Architecture Overview
Stratix II GX transceivers meet CEI jitter generation specification of 0.3 UI for a V
The Sinusoidal Jitter Tolerance Mask is defined only for low voltage (LV) variant of CPRI.
The jitter numbers for SONET/SDH are compliant to the GR-253-CORE Issue 3 Specification.
The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10.
The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
Symbol/
Table
4–19:
Clock (MHz)
Reference
156.25
622.08
156.25
62.5
100
125
chapter in volume 2 of the Stratix II GX Device Handbook.
Conditions
Table 4–20
each mode.
Type/Model
LVPECL XO
VCC6-Q/R
VCC6-Q/R
VCC6-Q/R
VCC6-Q/R
VCC6-Q/R
VCC6-Q
Vectron
provides information on recommended input clock jitter for
Commercial Speed
Min
-3 Speed
Range (MHz)
Grade
Frequency
270 to 800
Typ
10 to 270
10 to 270
10 to 270
10 to 270
10 to 270
Max
Notes
(12 kHz to 20
Min
RMS Jitter
Commercial and
Industrial Speed
MHz) (ps)
(1), (2),
0.3
0.3
0.3
0.3
0.3
-4 Speed
2
Grade
Typ
(3)
Max
OD
Period Jitter
Peak) (ps)
(Part 19 of 19)
(Peak to
range of 400 mV to 1000 mV.
23
23
30
23
23
23
Commercial Speed
Min
R
interoperability point.
Stratix II GX Transceiver
Altera Corporation
-5 Speed
T
Grade
Typ
interoperability point.
Phase Noise
Not available
-149.9957
-146.2169
-149.9957
-146.9957
-146.2169
(dB c/Hz)
at 1 MHz
June 2009
Max
Unit