XA3S100E-4TQG144Q Xilinx Inc, XA3S100E-4TQG144Q Datasheet
XA3S100E-4TQG144Q
Specifications of XA3S100E-4TQG144Q
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XA3S100E-4TQG144Q Summary of contents
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R DS635 (v2.0) September 9, 2009 Summary The Xilinx® Automotive (XA) Spartan®-3E family of FPGAs is specifically designed to meet the needs of high-volume, cost-sensitive automotive electronics applications. The five-member family offers densities ranging from 100,000 to 1.6 million system ...
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... The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XA3S100E has only one DCM at the top and bottom, while the XA3S1200E and XA3S1600E add two DCMs in the mid- dle of the left and right sides. ...
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... Notes: 1. The XA3S1200E and XA3S1600E have two additional DCMs on both the left and right sides as indicated by the dashed lines. The XA3S100E has only one DCM at the top and one at the bottom. Configuration XA Spartan-3E FPGAs are programmed by loading config- uration data into robust, reprogrammable, static CMOS con- figuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA’ ...
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... R XA Spartan-3E FPGAs support the following differential standards: • LVDS • Bus LVDS • mini-LVDS • RSDS Table 2: Available User I/Os and Differential (Diff) I/O Pairs Package VQG100 Size (mm Device User Diff User XA3S100E (7) (2) (11 XA3S250E (7) (2) (7) 92 XA3S500E - - (7) XA3S1200E - - - XA3S1600E - - ...
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R Package Marking Figure 2 provides a top marking example for XA Spartan-3E FPGAs in the quad-flat packages. marking for XA Spartan-3E FPGAs in BGA packages except the 132-ball chip-scale package (CPG132). The markings for the BGA packages are nearly ...
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... All devices are available in either I-Grade or Pb-Free Packaging Example: XA3S250E -4 FT Device Type Speed Grade Package Type Device Speed Grade XA3S100E -4 Only XA3S250E XA3S500E XA3S1200E XA3S1600E DS635 (v2.0) September 9, 2009 Product Specification Q-Grade temperature ranges. Only the -4 speed grade is available for the XA Spartan-3E family ...
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R Power Supply Specifications Table 3: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes and V supplies ...
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R DC Specifications Table 6: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX ΔV (2) Voltage variance on V CCAUX (3,4,5,6) V ...
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... This parameter is based on characterization. The pull-up resistance R Table 8: Quiescent Supply Current Characteristics Symbol Description I Quiescent V XA3S100E CCINTQ CCINT supply current XA3S250E XA3S500E XA3S1200E XA3S1600E I Quiescent V XA3S100E CCOQ CCO supply current XA3S250E XA3S500E XA3S1200E XA3S1600E DS635 (v2.0) September 9, 2009 Product Specification Test Conditions CCO ...
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... R Table 8: Quiescent Supply Current Characteristics (Continued) Symbol Description I Quiescent V XA3S100E CCAUXQ CCAUX supply current XA3S250E XA3S500E XA3S1200E XA3S1600E Notes: 1. The numbers in this table are based on the conditions set forth in 2. Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled ...
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R Single-Ended I/O Standards Table 9: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V for Drivers CCO IOSTANDARD Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4,5) LVCMOS25 2.3 LVCMOS18 1.65 LVCMOS15 1.4 LVCMOS12 1.1 PCI33_3 ...
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R Table 10: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions IOSTANDARD Attribute (mA) (mA) (3) LVTTL 2 2 – – – – – ...
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R Differential I/O Standards Table 11: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO IOSTANDARD Attribute Min (V) LVDS_25 2.375 BLVDS_25 2.375 MINI_LVDS_25 2.375 (2) LVPECL_25 RSDS_25 2.375 DIFF_HSTL_I_18 1.7 DIFF_HSTL_III_18 1.7 DIFF_SSTL18_I 1.7 DIFF_SSTL2_I 2.3 ...
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... DCM Table 19 and are based on the operating conditions set forth in www.xilinx.com V = 2.5V CCO DS635_05_082807 -4 Speed Grade Device Max Units XA3S100E 2.79 ns 3.45 ns XA3S250E 3.46 ns XA3S500E 3.46 ns XA3S1200E XA3S1600E 3.45 ns 5.92 ns XA3S100E 5.43 ns XA3S250E 5.51 ns XA3S500E 5.94 ns XA3S1200E 6.05 ns XA3S1600E Table 18. 14 ...
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... XA3S500E 4.02 ns XA3S1200E 5.52 ns XA3S1600E 4.46 ns XA3S100E –0.52 ns XA3S250E 0.14 ns XA3S500E 0.14 ns XA3S1200E 0.15 ns XA3S1600E 0.14 ns XA3S100E –0.24 ns XA3S250E –0.32 ns XA3S500E –0.49 ns XA3S1200E –0.63 ns XA3S1600E –0.39 ns 17. If this is true of the data Input, add the 17. If this is true of the data Input, subtract 15 ...
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... IFD_ Grade DELAY_ VALUE Device Min 0 All 2.12 2 XA3S100E 6.49 3 XA3S250E 6.85 2 XA3S500E 7.01 5 XA3S1200E 8.67 4 XA3S1600E 7.69 0 All –0.76 2 XA3S100E –3.93 3 XA3S250E –3.51 2 XA3S500E –3.74 5 XA3S1200E –4.30 4 XA3S1600E –4.14 All 1.80 and are based on the operating conditions set forth in Units ...
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... These adjustments are used to convert input path times originally specified for the LVCMOS25 standard to times that correspond to other signal standards. www.xilinx.com -4 Speed IFD_ Grade DELAY_ VALUE Device Max 0 All 2.25 2 XA3S100E 5.97 3 XA3S250E 6.33 2 XA3S500E 6.49 5 XA3S1200E 8.15 4 XA3S1600E 7.16 and are based on the operating conditions set forth in ...
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R Table 18: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...
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R Table 19: Test Methods for Timing Measurement at I/Os Signal Standard (IOSTANDARD) V REF Single-Ended LVTTL - LVCMOS33 - LVCMOS25 - LVCMOS18 - LVCMOS15 - LVCMOS12 - PCI33_3 Rising - Falling HSTL_I_18 0.9 HSTL_III_18 1.1 SSTL18_I 0.9 SSTL2_I 1.25 ...
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R Configurable Logic Block Timing Table 20: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, the time from the active CKO transition at the CLK input to data appearing at the XQ (YQ) output ...
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R Table 21: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on the SHCKO distributed RAM output Setup Times T Setup time of data at the BX ...
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R Clock Buffer/Multiplexer Switching Characteristics Table 23: Clock Distribution Switching Characteristics Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input ...
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R Table 24 Embedded Multiplier Timing (Continued) Symbol Clock Frequency F Internal operating frequency for a two-stage 18x18 multiplier using the MULT AREG and BREG input registers and the PREG output register Notes: 1. Combinatorial delay is ...
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R Table 25: Block RAM Timing (Continued) Symbol Clock Timing T High pulse width of the CLK signal BPWH T Low pulse width of the CLK signal BPWL Clock Frequency F Block RAM clock frequency. RAM read output value written ...
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R Delay-Locked Loop Table 26: Recommended Operating Conditions for the DLL Symbol Input Frequency Ranges F CLKIN_FREQ_DLL Frequency of the CLKIN clock input CLKIN Input Pulse Requirements CLKIN_PULSE CLKIN pulse width as a percentage of the CLKIN period Input Clock ...
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R Table 27: Switching Characteristics for the DLL (Continued) Symbol (4) Duty Cycle CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree duty-cycle distortion (4) Phase Alignment CLKIN_CLKFB_PHASE ...
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R Table 29: Switching Characteristics for the DFS Symbol Output Frequency Ranges CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs (2,3) Output Clock Jitter CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs (5,6) Duty Cycle CLKOUT_DUTY_CYCLE_FX Duty cycle precision ...
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R Table 31: Switching Characteristics for the PS in Variable Phase Mode Symbol Phase Shifting Range (2) MAX_STEPS Maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period in ns. If using ...
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... This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes. DS635 (v2.0) September 9, 2009 Product Specification Description , V , and V XA3S100E CCINT CCAUX CCO XA3S250E XA3S500E XA3S1200E XA3S1600E All XA3S100E XA3S250E XA3S500E XA3S1200E XA3S1600E All All Table 6. This means power must be applied to all V www.xilinx.com -4 Speed Grade Device Min Max - ...
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R Configuration Clock (CCLK) Characteristics Table 34: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T ConfigRate setting CCLK1 T CCLK3 T CCLK6 T CCLK12 T CCLK25 T CCLK50 Notes: 1. Set the ...
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R Master Serial and Slave Serial Mode Timing Table 38: Timing for the Master Serial and Slave Serial Configuration Modes Symbol Clock-to-Output Times T The time from the falling transition on the CCLK pin to data CCO appearing at the ...
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R Slave Parallel Mode Timing Table 39: Timing for the Slave Parallel Configuration Mode Symbol Clock-to-Output Times T The time from the rising transition on the CCLK pin to a signal transition at the SMCKBY BUSY pin Setup Times T ...
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R Serial Peripheral Interface Configuration Timing Table 40: Timing for SPI Configuration Mode Symbol T Initial CCLK clock period CCLK1 T CCLK clock period after FPGA loads ConfigRate setting CCLKn T Setup time on VS[2:0] and M[2:0] mode pins before ...
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R Byte Peripheral Interface Configuration Timing Table 42: Timing for BPI Configuration Mode Symbol T Initial CCLK clock period CCLK1 T CCLK clock period after FPGA loads ConfigRate setting CCLKn T Setup time on CSI_B, RDWR_B, and M[2:0] mode pins ...
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R IEEE 1149.1/1553 JTAG Test Access Port Timing Table 44: Timing for the JTAG Test Access Port Symbol Clock-to-Output Times T The time from the falling transition on the TCK pin TCKTDO to data appearing at the TDO pin Setup ...
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R Revision History The following table shows the revision history for this document. Date Version 08/31/07 1.0 Initial Xilinx release. • Updated 01/20/09 1.1 • Updated T • Updated description of T • Removed Table 45: MultiBoot Trigger Timing. • ...
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R Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE ...