XA3S100E-4TQG144Q Xilinx Inc, XA3S100E-4TQG144Q Datasheet - Page 2

• Manufacturer Part Number: XA3S100E-4TQG144Q
• Description: IC FPGA SPARTAN-3E 100K 144-TQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3E XAr

Specifications of XA3S100E-4TQG144Q

• Number Of Logic Elements/cells: 2160
• Number Of Labs/clbs: 240
• Total Ram Bits: 73728
• Number Of I /o: 108
• Number Of Gates: 100000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Key Feature Differences from Commercial XC Devices
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Table 1: Summary of XA Spartan-3E FPGA Attributes
Notes:
1.
Architectural Overview
The XA Spartan-3E family architecture consists of five fun-
damental programmable functional elements:
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DS635 (v2.0) September 9, 2009
Product Specification
XA3S100E
XA3S250E
XA3S500E
XA3S1200E
XA3S1600E
Device
AEC-Q100 device qualification and full production part
approval process (PPAP) documentation support
available in both extended temperature I- and
Q-Grades
Guaranteed to meet full electrical specification over the
T
XA Spartan-3E devices are available in the -4 speed
grade only.
PCI-66 is not supported in the XA Spartan-3E FPGA
product line.
The readback feature is not supported in the XA
By convention, one Kb is equivalent to 1,024 bits.
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
J
= –40°C to +125°C temperature range (Q-Grade)
R
System
1200K
1600K
Gates
100K
250K
500K
Equivalent
10,476
19,512
33,192
Logic
2,160
5,508
Cells
Rows Columns
22
34
46
60
76
(One CLB = Four Slices)
16
26
34
46
58
CLB Array
CLBs
1,164
2,168
3,688
Total
240
612
www.xilinx.com
14,752
Slices
2,448
4,656
8,672
Total
960
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These elements are organized as shown in
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XA3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XA3S100E has only one DCM at the top and bottom, while
the XA3S1200E and XA3S1600E add two DCMs in the mid-
dle of the left and right sides.
The XA Spartan-3E family features a rich network of traces
that interconnect all five functional elements, transmitting
signals among them. Each functional element has an asso-
ciated switch matrix that permits multiple connections to the
routing.
Distributed
RAM bits
136K
231K
15K
38K
73K
Spartan-3E FPGA product line.
XA Spartan-3E devices are available in Step 1 only.
JTAG configuration frequency reduced from 30 MHz to
25 MHz.
Platform Flash is not supported within the XA family.
XA Spartan-3E devices are available in Pb-free
packaging only.
MultiBoot is not supported in XA versions of this
product.
The XA Spartan-3E device must be power cycled prior
to reconfiguration.
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
(1)
Block
bits
216K
360K
504K
648K
RAM
72K
(1)
Multipliers DCMs
Dedicated
12
20
28
36
4
2
8
4
4
8
Maximum
User I/O
108
172
190
304
376
Figure
Differential
Maximum
I/O Pairs
1. A ring
124
156
40
68
77
2