XC3S500E-4PQG208I Xilinx Inc, XC3S500E-4PQG208I Datasheet - Page 110

• Manufacturer Part Number: XC3S500E-4PQG208I
• Description: IC FPGA SPARTAN-3E 500K 208-PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4PQG208I

• Package / Case: 208-MQFP, 208-PQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 158
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• No. Of Logic Blocks: 1564
• No. Of Gates: 500000
• No. Of Macrocells: 10476
• Family Type: Spartan-3E
• No. Of Speed Grades: 4
• No. Of I/o's: 158
• Clock: RoHS Compliant
• Total Ram Bits: 368640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional Description
Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
110
DonePin
DriveDone
DonePipe
ProgPin
TckPin
TdiPin
TdoPin
TmsPin
UserID
Security
Option Name
Pins/Function
reconfiguration
JTAG TCK pin
JTAG TDO pin
JTAG TMS pin
JTAG User ID
JTAG TDI pin
PROG_B pin
SelectMAP,
Readback,
DONE pin
DONE pin
DONE pin
Affected
register
Partial
JTAG,
(default)
Pulldown
Pulldown
Pulldown
Pulldown
Pullnone
Pullnone
Pullnone
Pullnone
Pullnone
Pullnone
Values
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Level1
Level2
string
None
User
Yes
Yes
No
No
Internally connects a pull-up resistor between DONE pin and V
330 Ω pull-up resistor to V
No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to V
is required.
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to V
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
The input path from DONE pin input back to the Startup sequencer is not pipelined.
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
Internally connects a pull-up resistor or between PROG_B pin and V
external 4.7 kΩ pull-up resistor to V
pull-up value may be weaker (see
No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
V
Internally connects a pull-up resistor between JTAG TCK pin and V
Internally connects a pull-down resistor between JTAG TCK pin and GND.
No internal pull-up resistor on JTAG TCK pin.
Internally connects a pull-up resistor between JTAG TDI pin and V
Internally connects a pull-down resistor between JTAG TDI pin and GND.
No internal pull-up resistor on JTAG TDI pin.
Internally connects a pull-up resistor between JTAG TDO pin and V
Internally connects a pull-down resistor between JTAG TDO pin and GND.
No internal pull-up resistor on JTAG TDO pin.
Internally connects a pull-up resistor between JTAG TMS pin and V
Internally connects a pull-down resistor between JTAG TMS pin and GND.
No internal pull-up resistor on JTAG TMS pin.
The 32-bit JTAG User ID register value is loaded during configuration. The default
value is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an
8-character hexadecimal value.
Readback and limited partial reconfiguration are available via the JTAG port or via the
SelectMAP interface, if the Persist option is set to Yes.
Readback function is disabled. Limited partial reconfiguration is still available via the
JTAG port or via the SelectMAP interface, if the Persist option is set to Yes.
Readback function is disabled. Limited partial reconfiguration is disabled.
CCAUX
is required.
www.xilinx.com
CCAUX
is still recommended.
Table
CCAUX
CCAUX
Description
78).
for a valid logic High.
is still recommended since the internal
DS312-2 (v3.8) August 26, 2009
CCAUX
Product Specification
CCAUX
CCAUX
CCAUX
CCAUX
CCAUX
. An external
.
.
.
.
. An
CCAUX
R