XC3S500E-4PQG208I Xilinx Inc, XC3S500E-4PQG208I Datasheet - Page 158

IC FPGA SPARTAN-3E 500K 208-PQFP

XC3S500E-4PQG208I

Manufacturer Part Number
XC3S500E-4PQG208I
Description
IC FPGA SPARTAN-3E 500K 208-PQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet

Specifications of XC3S500E-4PQG208I

Package / Case
208-MQFP, 208-PQFP
Mounting Type
Surface Mount
Voltage - Supply
1.1 V ~ 3.465 V
Operating Temperature
-40°C ~ 100°C
Number Of I /o
158
Number Of Logic Elements/cells
*
Number Of Gates
*
No. Of Logic Blocks
1564
No. Of Gates
500000
No. Of Macrocells
10476
Family Type
Spartan-3E
No. Of Speed Grades
4
No. Of I/o's
158
Clock
RoHS Compliant
Total Ram Bits
368640
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S500E-4PQG208I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S500E-4PQG208I
0
DC and Switching Characteristics
Byte Peripheral Interface (BPI) Configuration Timing
Table 120: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
158
T
T
T
T
T
T
T
T
(Open-Drain)
Symbol
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
PROG_B
LDC[2:0]
HSWAP
CSO_B
A[23:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
D[7:0]
CCLK
HDC
Figure 78: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration (BPI-DN mode shown)
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on CSI_B, RDWR_B, and M[2:0] mode pins before the rising
edge of INIT_B
Hold time on CSI_B, RDWR_B, and M[2:0] mode pins after the rising
edge of INIT_B
Minimum period of initial A[23:0] address cycle;
LDC[2:0] and HDC are asserted and valid
Address A[23:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
T
MINIT
<0:1:0>
HSWAP must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if HSWAP input is Low.
Pin initially high-impedance (Hi-Z) if HSWAP input is High.
Description
000_0000
T
CCLK1
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
Byte 0
T
INITADDR
000_0001
(M[2:0]=<0:1:0>)
(M[2:0]=<0:1:1>)
BPI-DN:
BPI-UP:
Byte 1
T
AVQV
Data
Minimum
New ConfigRate active
T
50
Address
CCLK1
0
5
2
T
DS312-3 (v3.8) August 26, 2009
CCO
Data
T
See
See
See
See
See
DCC
T
Maximum
Product Specification
CCLKn
Table 112
Table 112
Table 116
Table 116
Table 116
Address
Data
5
2
-
-
DS312-3_08_032409
Address
T
CCD
T
cycles
Units
Data
CCLK1
ns
ns
R

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