XC3S500E-4PQG208I Xilinx Inc, XC3S500E-4PQG208I Datasheet - Page 29

• Manufacturer Part Number: XC3S500E-4PQG208I
• Description: IC FPGA SPARTAN-3E 500K 208-PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4PQG208I

• Package / Case: 208-MQFP, 208-PQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 158
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• No. Of Logic Blocks: 1564
• No. Of Gates: 500000
• No. Of Macrocells: 10476
• Family Type: Spartan-3E
• No. Of Speed Grades: 4
• No. Of I/o's: 158
• Clock: RoHS Compliant
• Total Ram Bits: 368640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14: Carry Logic Functions
DS312-2 (v3.8) August 26, 2009
Product Specification
CYINIT
CY0F
CY0G
CYMUXF
Function
R
G[4:1]
F[4:1]
Initializes carry chain for a slice. Fixed selection of:
• CIN carry input from the slice below
• BX input
Carry generation for bottom half of slice. Fixed selection of:
• F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated)
• FAND gate for multiplication
• BX input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
Carry generation for top half of slice. Fixed selection of:
• G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated)
• GAND gate for multiplication
• BY input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of:
• CYINIT carry propagation (CYSELF = 1)
• CY0F carry generation (CYSELF = 0)
BY
BX
4
G1
F1
G2
F2
GAND
FAND
A[4:1]
A[4:1]
G-LUT
F-LUT
Figure 22: Carry Logic
D
D
1
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1
CYSELG
1
0
1
CYSELF
0
CY0G
CY0F
COUT
Description
CYMUXG
CIN
CYMUXF
CYINIT
XORG
XORF
FFY
FFX
Functional Description
DS312-2_14_021305
YQ
YB
Y
XQ
XB
X
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