XC3S500E-4PQG208I Xilinx Inc, XC3S500E-4PQG208I Datasheet - Page 161

• Manufacturer Part Number: XC3S500E-4PQG208I
• Description: IC FPGA SPARTAN-3E 500K 208-PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4PQG208I

• Package / Case: 208-MQFP, 208-PQFP
• Mounting Type: Surface Mount
• Voltage - Supply: 1.1 V ~ 3.465 V
• Operating Temperature: -40°C ~ 100°C
• Number Of I /o: 158
• Number Of Logic Elements/cells: *
• Number Of Gates: *
• No. Of Logic Blocks: 1564
• No. Of Gates: 500000
• No. Of Macrocells: 10476
• Family Type: Spartan-3E
• No. Of Speed Grades: 4
• No. Of I/o's: 158
• Clock: RoHS Compliant
• Total Ram Bits: 368640
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision History
The following table shows the revision history for this document.
DS312-3 (v3.8) August 26, 2009
Product Specification
03/01/05
11/23/05
03/22/06
04/07/06
05/19/06
05/30/06
11/09/06
03/16/07
05/29/07
Date
R
Version
3.2.1
1.0
2.0
3.0
3.1
3.2
3.4
3.5
3.6
Initial Xilinx release.
Added AC timing information and additional DC specifications.
Upgraded data sheet status to Preliminary. Finalized production timing parameters. All
speed grades for all Spartan-3E FPGAs are now Production status using the v1.21 speed
files, as shown in
and clock-to-output timing based on final characterization, shown in
system-synchronous input setup and hold times based on final characterization, shown in
Table 87
adjustments for LVPECL_25, DIFF_SSTL and DIFF_HSTL I/O standards that supersede
the v1.21 speed file values, in
delays in
slice flip-flop timing by 100 ps in
SRL16 timing in
in
remainder of Step 0 device; added improved Step 1 DCM performance to
Table
T
Table
Table
MultiBoot timing specifications to
Improved SSO limits for LVDS_25, MINI_LVDS_25, and RSDS_25 I/O standards in the QFP
packages
Clarified that 100 mV of hysteresis applies to LVCMOS33 and LVCMOS25 I/O standards
(Note 4,
Corrected various typos and incorrect links.
Improved absolute maximum voltage specifications in
overshoot allowance. Widened the recommended voltage range for PCI and PCI-X
standards in
v1.26 speed file. Added
time all devices became Production status. Added absolute minimum values for
Table
IFD_DELAY_VALUE settings in
source-synchronous input capture sample window. Promoted Module 3 to Production
status. Synchronized all modules to v3.4.
Based on extensive 90 nm production data, improved (reduced) the maximum quiescent
current limits for the I
of 50%.
Added note to
t
MHz for Stepping 1 in
RPW_CLB
INIT
Table
, in
105,
117. Improved the DCM performance for the XC3S1200E, Stepping 0 in
105,
92, and
Table
101. Updated block RAM timing in
Table
and
Table
in
(Table
Table
Table
Table 98
Table
Table
111. Increased data hold time for Slave Parallel mode to 1.0 ns (T
Table
80). Other minor edits.
Table 74
93. Added XC3S100E FPGA in CP132 package to
Table
106, and
106, and
97). Removed potentially confusing Note 2 from
Table
80. Clarified Note 2,
88. Updated other I/O timing in
93. Updated pin-to-pin setup and hold timing based on default
CCINTQ
to match value in speed file. Improved CLKOUT_FREQ_CLK90 to 200
100. Updated global clock timing, removed left/right clock buffer limits
Table
www.xilinx.com
Table 85
84. Expanded description in Note 2,
and
Table
Table
, I
Table 75
105.
Table 91
CCAUXQ
Table
Table
107. Added minimum INIT_B pulse width specification,
107. Corrected links in
to summarize the history of speed file releases after which
Table
regarding HSWAP in step 0 devices. Updated
, and I
87,
98. Updated distributed RAM timing in
and
Table
122.
Revision
Table
Table
Table
CCOQ
83. Improved various timing specifications for
88, and
94. Reduced I/O three-state and set/reset
103. Added DCM parameters for
specifications in
Table
Table
DC and Switching Characteristics
Table 118
Table
90. Provided input and output
73, providing additional
Table
90. Added
Table
Table
and
78. Updated pin-to-pin
Table 79
Table
Table
78.
96. Increased T
Table 89
Table
86. Updated
by an average
120. Added
Table 99
Table
104,
SMCCD
Table
about
104,
and
86,
) in
AS
161