XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 16

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

XC2000 Logic Cell Array Families
Master Serial Mode
Figure 13. Master Serial Mode
In Master Serial mode, the CCLK output of the lead LCA
device drives a Xilinx Serial PROM that feeds the LCA DIN
input. Each rising edge of the CCLK output increments the
Serial PROM internal address counter. This puts the next
data bit on the SPROM data output, connected to the LCA
DIN pin. The lead LCA device accepts this data on the
subsequent rising CCLK edge.
The lead LCA device then presents the preamble data
(and all data that overflows the lead device) on its
DOUT pin.
DURING CONFIGURATION
THE 5 k M2 PULL-DOWN
THE INTERNAL PULL-UP,
RESISTOR OVERCOMES
BUT IT ALLOWS M2 TO
*
SERIES WITH M1
IS REQUIRED IN
IF READBACK IS
5-k RESISTOR
ACTIVATED, A
BE USER I/O.
GENERAL-
PURPOSE
USER I/O
RESET
DONE
PINS
DOUT
M2
HDC
RESET
D/P
LDC
M0
OTHER
I/O PINS
*
M1
(LOW RESETS THE XC17XX ADDRESS POINTER)
LCA
PWRDWN
+5 V
CCLK
2-200
LDC
DIN
There is an internal delay of 1.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge.
The SPROM CE input should be driven from LDC . Using
LDC avoids potential contention on the DIN pin, if this pin
is configured as user-I/O, but LDC is then restricted to be
a permanently High user output. Using DONE causes
contention on DIN because there is no “early DONE”
option on XC2000 devices.
DATA
CLK
CE
OE
OPTIONAL
DAISY-CHAINED
LCAs WITH
DIFFERENT
CONFIGURATIONS
+5 V
V CC
OPTIONAL
SLAVE LCAs
WITH IDENTICAL
CONFIGURATIONS
XC17XX
SCP
V PP
CEO
CASCADED
MEMORY
SERIAL
X3033