XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 31

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

MASTER-SER
M1 (LOW)
M0 (LOW)
M2 (LOW)
CCLK (0)
<0:0:0>
RCLK
<<HIGH>>
<<HIGH>> IS HIGH IMPEDANCE WITH A 20-50 k INTERNAL PULL-UP DURING CONFIGURATION
M1 (HIGH)
M0 (HIGH)
<<HIGH>>
<<HIGH>>
CCLK (I)
<1:1:1>
SLAVE
DIN (I)
XC2018 Configuration Pin Assignments
CONFIGURATION MODE: <M2:M1:M0>
PERIPHERAL
PWRDWN (I)
HDC (HIGH)
LDC (LOW)
<<HIGH>>
<<HIGH>>
M1 (LOW )
M0 (HIGH)
<<HIGH>>
<<HIGH>>
<<HIGH>>
<<HIGH>>
RESET (I)
DONE (O)
DOUT (O)
WRT (I)
<1:0:1>
CSO (I)
CS1 (I)
CS2 (I)
GND
GND
V
CC
M2 (HIGH)
CCLK (O)
V
CC
MASTER-HIGH
M1 (HIGH)
M0 (LOW)
<1:1:0>
A13 (O)
A6
A12 (O)
A7
A11 (O)
A8
A10 (O)
A9
A0
A1
A2
A3
A15 (O)
A4
A14 (O)
A5
RCLK
D7 (I)
D6 (I)
D5 (I)
D4 (I)
D3 (I)
D2 (I)
D1 (I)
D0 (I)
2-215
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
(O)
MASTER-LOW
M1 (LOW)
M0 (LOW)
<1:0:0>
PLCC
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
VQFP
64
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
8
9
1
2
3
4
5
6
7
PLCC
68
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
PLCC
84
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
9
PGA
K10
K11
H10
H11
G10
G11
E11
E10
D11
D10
C11
B11
C10
A11
B10
A10
L10
L11
J10
J11
F10
F11
G3
G1
G2
G9
84
C6
A6
A5
B5
C5
A4
B4
A3
A2
B3
A1
B2
C2
B1
C1
D2
D1
E3
E2
E1
F2
F3
F1
H1
H2
K1
L1
K2
K3
L2
L3
K4
L4
K5
L5
K6
L7
K7
L6
L8
K8
L9
K9
F9
E9
B9
A9
B8
A8
B6
B7
A7
C7
J1
J2
J5
J6
J7
TQFP
100
1 5
13
14
16
17
18
19
20
21
22
23
26
27
29
30
32
33
34
35
36
37
38
39
40
41
42
43
45
47
48
49
51
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
75
77
78
79
80
82
84
85
86
87
88
89
90
91
92
93
95
96
97
98
99
10
11
12
2
3
5
6
7
8
9
OPERATION
XTL2 OR I/O
XTL1 OR I/O
PWR DWN
RDATA (O)
RTRIG (I)
PROG (I)
CCLK (I)
RESET
USER
GND
GND
V
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CC
CC
X3461