XC2018-70PC84C Xilinx Inc, XC2018-70PC84C Datasheet - Page 26

• Manufacturer Part Number: XC2018-70PC84C
• Description: IC LOGIC CL ARRAY 1800GAT 84PLCC
• Manufacturer: Xilinx Inc
• Series: XC2000r

Specifications of XC2018-70PC84C

• Number Of Labs/clbs: 100
• Total Ram Bits: 17878
• Number Of I /o: 74
• Number Of Gates: 1500
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-LCC (J-Lead)
• Dc: 93+
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1004

XC2000 Logic Cell Array Families
because of the table look-up based implementation. Tim-
ing is different when the combinatorial logic is used in
conjunction with the storage element. For the combinato-
rial logic function driving the data input of the storage
element, the critical timing is data set-up relative to the
clock edge provided to the storage element. The delay
from the clock source to the output of the logic block is
critical in the timing of signals produced by storage ele-
ments. The loading on a logic block output is limited only
by the additional propagation delay of the interconnect
network. Performance of the logic block is a function of
supply voltage and temperature, as shown in Figure 19 .
Interconnect Performance
Interconnect performance depends on the routing re-
source used to implement the signal path. As discussed
earlier, direct interconnect from block to block provides a
minimum delay path for a signal.
The single metal segment used for Longlines exhibits low
resistance from end to end, but relatively high capa-
citance. Signals driven through a programmable switch
will have the additional impedance of the switch added to
their normal drive impedance.
General-purpose interconnect performance depends on
the number of switches and segments used, the presence
of the bidirectional repowering buffers and the overall
Figure 19. Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
1.00
0.80
0.60
0.40
0.20
– 55
– 40
– 20
0
TYPICAL COMMERCIAL
TYPICAL MILITARY
(+ 5.0 V, 25°C)
TEMPERATURE (°C)
2-210
25
loading on the signal path at all points along the path. In
calculating the worst-case delay for a general interconnect
path, the delay calculator portion of the XACT develop-
ment system accounts for all of these elements. As an
approximation, interconnect delay is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the delay is a sum of R-C
delays each approximated by an R times the total C it
drives. The R of the switch and the C of the interconnect
are functions of the particular device performance grade.
For a string of three local interconnects, the approximate
delay at the first segment, after the first switch resistance,
would be three units; an additional two delay units after the
next switch plus an additional delay after the last switch in
the chain. The interconnect R-C chain terminates at each
repowering buffer. Nearly all of the capacitance is in the
interconnect metal and switches; the capacitance of the
block inputs is not significant.
Power
Power Distribution
Power for the LCA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
For packages having more than 48 pins, two V
two ground pins are provided (see Figure 20). Inside the
LCA device, a dedicated V
the logic array provides power to the I/O drivers. An
40
70
SPECIFIED WORST-CASE VALUES
80
CC
and ground ring surrounding
100
125
CC
pins and
X1045