AT43USB325E-AC Atmel, AT43USB325E-AC Datasheet
AT43USB325E-AC
Specifications of AT43USB325E-AC
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AT43USB325E-AC Summary of contents
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... AT43USB325 extremely suitable for key- boards supporting the consumer page as described in the “USB Usage Tables” AT43USB325E is an SRAM that is automatically written from an external serial EEPROM during power on. The AT43USB325M has a masked ROM program mem- ory. The two versions are pin, function and binary compatible. ...
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... Pin Configuration Figure 1-1. 64-lead LQFP AT43USB325E-AC PD3 PD1 PD0 DP0 DM0 DP2 DM2 DP3 DM3 VCC1 CEXT1 VSS1 DP4 DM4 DP5 DM5 Figure 1-2. 64-lead LQFP AT43USB325M-AC PD3 PD1 PD0 DP0 DM0 DP2 DM2 DP3 DM3 VCC1 CEXT1 VSS1 ...
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Pin Assignment Pin# Signal 1 PD3 2 PD1 3 PD0 4 DP0 5 DM0 6 DP2 7 DM2 8 DP3 9 DM3 10 VCC1 Power Supply/Ground 11 CEXT1 12 VSS1 Power Supply/Ground 13 DP4 14 DM4 15 DP5 16 ...
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Signal Description Name Type V Power Supply/Ground CC1, 2 CEXT1, 2 Output V , Power Supply/Ground SS1 2 XTAL1 Input XTAL2 Output LFT Input DPO Bi-directional DMO Bi-directional DP[2:5] Bi-directional DM[2:5] Bi-directional PA[0:7] Bi-directional PB[0:7] Bi-directional PC[0:7] Bi-directional PD[0,1,3:7] ...
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... SI, SPI Slave Data Input PF3 SO, SPI Slave Data Out No Connect/Slave Select – In the AT43USB325M this pin is not used. In the AT43USB325E this pin is the SPI slave select input used for enabling the serial memory during program memory downloading. Test Pin – This pin should be tied to ground. ...
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Figure 1-3. AT43USB325 Enhanced RISC Architecture with USB Keyboard Controller and Hub Program Memory Instruction Register Instruction Decoder Control Lines AT43USB325 6 Program Status and Counter Control General-purpose Registers ALU 512 x 8 SRAM ...
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... Data Space addresses ($ F), allowing them to be accessed as though they were ordinary memory locations. 3355C–USB–4/05 page 17 summarizes the available I/O registers. The “AVR Register Set” on covers the AVR registers. Please refer to the Atmel AVR manual for more information. AT43USB325 ™ Microcon- Figure 1-3 on page 6 ...
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The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, Timer/Counters, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the register file, $20 ...
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General-purpose Register File Table 3-1. Register R13 R14 R15 R16 R17 .. R26 R27 R28 R29 R30 R31 All register operating instructions in the instruction set have direct and single cycle access to all registers. ...
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... Constant tables can be allocated within the entire program memory address space (see the LPM - Load Program Memory instruction description). The program memory of the AT43USB325E is automatically written with data stored in an exter- nal serial EEPROM during the chip's power on reset sequence. The power on reset is the only way the on-chip program memory of the AT43USB325E will be written or modified ...
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... Figure 3-1. 3.4.1 Read Sequence 1. The AT43USB325E asserts its SSN output pin and outputs a 3 MHz clock at SCK. It continues to activate SCK until the completion of the read process. 2. The AT43USB325E transmits the READ opcode (= 0000011) through its MOSI, fol- lowed by the 16-bit byte address to be read, x0000. Please note that the AT43USB325E will send a 16-byte address only ...
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SRAM Data Memory Table 3-3 Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first 96 locations address the Register File + I/O Memory, and the next 512 locations address the internal data ...
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Table 3-2. 3355C–USB–4/05 SRAM Organization Register File R0 R1 R30 R31 I/O Registers $00 $01 $3E $3F AT43USB325 Data Address Space $0000 $0001 $001E $001F $0020 $0021 $005E $005F Internal SRAM $0060 $0061 $025E $045F USB Registers $1F00 $1FFE $1FFF ...
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Table 3-3. Address $1FFD $1FFC $1FFB $1FFA $1FF9 $1FF8 $1FF7 $1FF6 $1FF5 $1FF3 $1FF2 $1FEF $1FEE $1FE7 $1FE5 $1FE4 $1FE3 $1FE2 $1FDF $1FDD $1FDC $1FDB $1FDA $1FD7 $1FD5 $1FD4 $1FD3 $1FD2 $1FCF $1FCD $1FCC $1FCB $1FCA $1FC7 $1FC5 $1FBC AT43USB325 ...
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Table 3-3. Address $1FBB $1FBA $1FB9 $1FB8 $1FB4 $1FB3 $1FB2 $1FB1 $1FB0 $1FAC $1FAB $1FAA $1FA9 $1FA7 $1FA5 $1FA4 $1FA3 $1FA2 3355C–USB–4/05 USB Hub and Function Registers (Continued) Name Function HPSTAT4 Hub Port 4 Status Register HPSTAT3 Hub Port 3 ...
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Table 3-4. USB Hub and Function Registers Name Address Bit 7 Bit 6 GLB_STATE $1FFB – KB INT EN SPRSR $1FFA INTD INTC SPRSIE $1FF9 INTD EN INTC EN SPRSMSK $1FF8 INTD MSK INTC MSK UISR $1FF7 SOF INT EOF2 ...
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Table 3-4. USB Hub and Function Registers (Continued) Name Address Bit 7 Bit 6 FCAR1 $1FA4 CTL DIR DATA END FCAR2 $1FA3 CTL DIR DATA END FCAR3 $1FA2 CTL DIR DATA END 3.6 I/O Memory The I/O space definition of ...
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Table 3-5. I/O (SRAM) Address $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22) $01 ($21) All AT43USB325 I/O and peripherals, except for the USB hardware registers, ...
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Figure 3-3. USB Hardware 3355C–USB–4/05 Port 0 XCVR Hub Repeater Serial Interface Engine Port 1 Hub Function Interface Interface Unit Unit AVR Microcontroller AT43USB325 Port 2 XCVR Port 3 XCVR Port 4 XCVR Port 5 XCVR Data Address Control 19 ...
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Functional Description 4.1 On-chip Power Supply The AT43USB325 contains two on-chip power supplies that generate 3.3V with a capacity each from the 5V power input. The on-chip power supplies are intended to supply the AT43USB325 internal ...
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Figure 4-1. 4.4 Reset and Interrupt Handling The AT43USB325 provides 12 different interrupt sources with 4 separate reset vectors, each with a separate program vector in the program memory space. Nine of the interrupt sources share 2 interrupt reset vectors. ...
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The most typical and general program setup for the Reset and Interrupt Vector Addresses are: Address $000 $002 $00E Overflow Handler $018 ; $00d start $00e $00f $010 $011 ... USB related interrupt events are routed to reset vectors 13 ...
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Figure 4-2. AT43USB325 Interrupt Structure SOF EOF2 FEP3 FEP2 FEP1 FEP0 HEP0 Suspend/Resume FRMWUP RSM GLB SUSP BUS RESET INTA INTB INTC INTD 4.5 Reset Sources The AT43USB325 has four sources of reset: • Power-on Reset – The MCU is ...
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Separated reset: A USB bus reset will only reset the USB hardware, while an When the USB hardware is reset, the compound device is de-configured and has to be re-enu- merated by the host. When the microcontroller is reset, ...
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External Reset An external reset is generated by a low-level on the RESET pin. Reset pulses longer than 200 ns will generate a reset. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the ...
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Non-USB Related Interrupt Handling The AT43USB325 has two non-USB 8-bit Interrupt Mask control registers; GIMSK (General Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all ...
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Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB325 and always read as zero. 4.9.2 General Interrupt Flag Register – GIFR Bit $3A ($5A) Read/Write Initial Value • Bit 7 – INTF1: External Interrupt ...
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CompareB match in Timer/Counter1 occurs, i.e., when the OCF1B bit is set in the TIFR. • Bit 4 – Res: Reserved Bit This bit is a reserved bit in the AT43USB325 and always reads zero. ...
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Alternatively, OCF1B is cleared by writing a logic one to the flag. When the I-bit in SREG, and OCIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare B ...
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MCU Control Register – MCUCR Bit $35 ($55) Read/Write Initial Value • Bit 7, 6 – Res: ...
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USB Interrupt Sources The USB interrupts are described below. Table 4-3. Interrupt SOF Received EOF2 Function EP0 Interrupt Function EP1 Interrupt Function EP2 Interrupt Function EP3 Interrupt Hub EP0 Interrupt FRWUP GLB SUSP RSM BUS RESET All interrupts have ...
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USB Endpoint Interrupt Sources An assertion or activation of one or more bits in the endpoint's Control and Status Register trig- gers the endpoint interrupts. These triggers are different for control and non-control endpoints as described in the table ...
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USB Interrupt Mask Register – UIMSKR Bit $1FF6 Read/Write Initial Value • Bit 7 – SOF IMSK: Enable Start of Frame Interrupt Mask When the SOF IMSK bit is set (1), the Start of Frame Interrupt is masked. • ...
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USB Interrupt Acknowledge Register – UIAR Bit $1FF5 Read/Write Initial Value • Bit 7 – SOF INTACK: Start of Frame Interrupt Acknowledge The microcontroller firmware writes this bit to clear the SOF INT bit. • Bit ...
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USB Interrupt Enable Register – UIER Bit $1FF3 Read/Write Initial Value • Bit 7 – SOF IE: Enable Start of Frame Interrupt When the SOF IE bit is set (1), the Start of Frame Interrupt is enabled. • Bit ...
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Suspend/Resume Register – SPRSR Bit $1FFA Read/Write Initial Value • Bit 7 – INTD: External Interrupt D The INTD bit is set when an external interrupt at the INTD pin is detected. • Bit 6 – INTC: External Interrupt ...
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Suspend/Resume Interrupt Enable Register – SPRSIE Bit $1FF9 Read/Write Initial Value • · Bit 7 – INTD EN: External Interrupt D Enable Setting the INTD EN bit will initiate an interrupt whenever the INTD bit of SPRSR is set. ...
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Suspend/Resume Interrupt Mask Register – SPRSMSK Bit $1FF8 Read/Write Initial Value The bits of the Suspend/Resume Mask Register are used to make an interrupt caused by an event in the Suspend/Resume Register visible to the µC. The Suspend/Resume Interrupt ...
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INTA/B/C/D Interrupt Sense Control Register – ISCR Bit $1FF1 Read/Write Initial Value • Bit 7,6 – ISC71, ISC70: External Interrupt D Sense Control Bits ISC71 and ISC70 controls the level and sense of the input at the INTD pin ...
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AVR Register Set 5.1 Status Register and Stack Pointer 5.1.1 Status Register – SREG Bit $3F ($5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the ...
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Stack Pointer Register – SP Bit $3E ($5E) $3D ($5D) Read/Write Initial Value The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must ...
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Timer/Counters The AT43USB325 provides two general-purpose Timer/Counters - one 8-bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescaling timer. Both Timer/Counters can either be used as a timer with an internal ...
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Timer/Counter0 The 8-bit Timer/Counter0 can select clock source from CK, prescaled external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Reg- ister (TCCR0). The overflow status flag ...
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Timer/Counter0 Control Register – TCCR0 Bit $33 ($53) Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT43USB325 and always read as zero. • Bits – CS02, CS01, ...
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Timer/Counter1 Figure 6-3. Timer/Counter1 Block Diagram T/C1 OVERFLOW IRQ TIMER INT. MASK REGISTER (TIMSK) 15 T/C1 INPUT CAPTURE REGISTER (ICR1) 15 TIMER/COUNTER1 (TCNT1) 15 16-BIT COMPARATOR 15 TIMER/COUNTER1 OUTPUT COMPARE REGISTER A 3355C–USB–4/05 T/C1 COMPARE T/C1 COMPARE MATCHB ...
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Timer/Counter1 Operation The 16-bit Timer/Counter1 can select clock source from CK, prescaled external pin. In addition, it can be stopped as described in the specification for the Timer/Counter1 Control Reg- isters (TCCR1A and TCCR1B). The ...
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Timer/Counter1 Control Register A – TCCR1A Bit $2F ($4F) Read/Write Initial Value • Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a ...
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Timer/Counter1 Control Register B – TCCR1B Bit $2E ($4E) Read/Write Initial Value • Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is dis- ...
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Table 6-4. CS12 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the 12 MHz system clock. If the external pin modes are used for Timer/Counter1, transitions on PB1/(T1) ...
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Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL Bit $2B ($4B) $2A ($4A) Read/Write Initial Value 6.4.5 Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL Bit $29 ($49) $28 ($48) Read/Write Initial Value The output compare registers are 16-bit ...
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Timer/Counter1 Input Capture Register – ICR1H and ICR1L Bit $25 ($45) $24 ($44) Read/Write Initial Value The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ...
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Table 6-6. COM1X1 Note: Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches the value TOP. This prevents the ...
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TOP value, making a one-period PWM pulse. Table 6-7. COM1X1 Note: In PWM mode, the Timer Overflow Flag1, TOV1, is set when the ...
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Watch Dog Timer Control Register – WDTCR Bit $21 ($41) Read/Write Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT43USB325 and will always read as zero. • Bit 4 – WDTOE: ...
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... LED drivers EEPROM Interface In the AT43USB325E Port F[0:3] are used as the SPI signals for the external serial EEPROM. Once the data from the SEEPROM are loaded to the SRAM, Port F[1:3] become available as GPIO pins. Only cycling the power to the chip off and on again will temporarily assign these pins as EEPOM signals. 3355C– ...
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Port A Port 8-bit bi-directional I/O port with open drain outputs and controlled slew rate designed for use as the column driver in a keyboard controller. The Port A output buffers can sink or ...
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Port B Port 8-bit bi-directional I/O port with open drain outputs and controlled slew rate designed for use as the column driver in a keyboard controller. The Port B output buffers can sink or ...
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Port C Port 8-bit bi-directional I/O port with an internal pull-up resistor at each pin. Port C is designed for use as the row inputs of a keyboard controller. Its output buffers can sink 4 mA. ...
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Port D Port 7-bit bi-directional I/O port. Three I/O memory address locations are allocated for the Port D, one each for the Data Register - PORTD, $12($32), Data Direction Register - DDRD, $11($31) and the Port ...
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Port D as General Digital I/O PDn, General I/O Pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is con-figured as an output pin. If DDDn is cleared ...
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Port E Input Pins Address – PINE Bit $01 ($21) Read/Write Initial Value The Port E Input Pins address, PINE, is not a register, and this address enables access to the physical value on each Port E pin. When ...
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Port F Data Register – PORTF Bit $06($26) Read/Write Initial Value 7.6.2 Port F Data Direction Register – DDRF Bit $05($25) Read/Write Initial Value 7.6.3 Port F Input Pin Address – PINF Bit $04($24) Read/Write Initial Value The Port ...
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Programming the USB Module The USB hardware consists of two devices, hub and function, each with their own device address and endpoints. Its operation is controlled through a set of memory mapped registers. The exact configuration of the USB ...
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Control Transfers at Control End-point EP0 The description given below is for the function control end-point, but applies to the hub control end-point as well if the proper registers are used. The following illustration describes the three possible types ...
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The following information describes how the AT43USB325’s USB hardware and firmware oper- ates during a control transfer between the host and the hub’s or function’s control end-point. Legend: 8.1.2 Idle State This is the default state from power-up. 3355C–USB–4/05 ( ...
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Setup Response State The Function Interface Unit (FIU) receives a SETUP token with 8 bytes of data from the Host. The FIU stores the data in the FIFO, sends an ACK back to the host and asserts an RX_SETUP ...
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No-data Status Response State The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero length DATA1 packet until receiving an ACK from the host, then asserts a TX_COMPLETE interrupt token ...
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Control Read Status Response State The Function Interface Unit receives an OUT token from the Host with a zero length DATA1 packet. The FIU responds with a NAK until TX_COMPLETE is cleared. The FIU will then ACK the retried ...
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Control Write Status Response State The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero length DATA1 packet, retrying until it receives an ACK back from the Host. The FIU then asserts ...
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Interrupt/Bulk OUT Transfers at Function End-point EP1, 2 and 3 The firmware must first condition the end-point through the End-point Control Register, FEND- P1/2/3_CNTR: Set end-point direction: clear EPDIR Set interrupt or bulk: EPTYPE = Enable ...
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USB Registers The following sections describe the registers of the AT43USB325’s USB hub and function units. Reading a bit for which the microcontroller does not have read access will yield a zero value result. Writing to a bit for ...
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Endpoint Registers 8.3.1 Hub Endpoint 0 Control Register – HENDP0_CR 8.3.2 Function Endpoint 0 Control Register – FENDP0_CR Bit $1FE7 $24 ($44) Read/Write Initial Value • Bit 7 – EPEN: Endpoint Enable 0 = Disable endpoint 1 = Enable ...
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Function Endpoint 1-3 Control Register – FENDP1-3_CR Bit $1FE4 $1FE3 $1FE2 Read/Write Initial Value • Bit 7 – EPEN: Endpoint Enable 0 = Disable endpoint 1 = Enable endpoint • Bit 6..4 – Reserved These bits are reserved in ...
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Hub Endpoint 0 Data Register – HDR0 8.3.5 Function Endpoint 0..3 Data Register – FDR0..3 Bit $1FD7 $1FD5 $1FD4 $1FD3 $1FD2 Read/Write Initial Value This register is used to read data from or to write data to the Hub ...
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Hub Endpoint 0 Byte Count Register – HBYTE_CNT0 8.3.7 Function Endpoint 0..3 Byte Count Register – FBYTE_CNT0..3 The contents of these registers stores the number of bytes to be sent or that was received by USB Hub and Function ...
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Hub Endpoint 0 Service Routine Register – HCSR0 8.3.9 Function Endpoint 0 Service Routine Register – FCSR0 Bit Function EP0 $1FDF Function EP0 $1FDD Read/Write Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB325 ...
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Hub Endpoint 0 Control and Acknowledge Register – HCAR0 8.3.11 Function Endpoint 0 Control and Acknowledge Register – FCAR0 Bit Hub EP0 $1FA7 Function EP0 $1FDD Read/Write Initial Value • Bit 7 – DIR: Control transfer direction It is ...
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The microcontroller should write into the FIFO only if this bit is cleared. After it has completed writing the data, it should set this bit. This data can be of zero length. Hardware clears this bit after it receives an ...
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Function Endpoint 1,2,3 Service Routine Register – FCSR1,2,3 Function EP1 $1FDC Function EP2 $1FDB Function EP3 $1FDA Read/Write Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB325 and will read as zero. • Bit ...
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Function Endpoint 1,2,3 Control and Acknowledge Register – FCAR1,2,3 Bit Function EP1 $1FA4 Function EP2 $1FA3 Function EP3 $1FA2 Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB325 and will read as zero. ...
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USB Hub The hub in a USB system provides for the electrical interface between USB devices and the host. The major functions that the hub must supports are: • Connectivity • Power management • Device connect and disconnect • ...
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Hub General Registers 8.4.1.1 Global State Register – GLB_STATE Bit $1FFB Read/Write Initial Value • Bit 7 – Reserved Bit This bit is reserved in the AT43USB325 and will read as zero. • Bit 6 – KB INT EN: ...
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Hub Status Register In the AT43USB325 overcurrent detection and port power switch control output processing is done in firmware. The hardware is designed so that various types of hubs are possible just through firmware modifications. 1. Hub local power ...
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Hub Port Control Register – HPCON Bit $1FC5 Read/Write Initial Value • Bit 7 – Reserved This bits is reserved in the AT43USB325 and will read as zero. • Bit 6..4 – HPCON2..0: Hub Port Control Command These bits ...
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These bits define which port is being addressed for the command defined by bits [2:0]. 8.4.3 Selective Suspend and Resume The host can selectively suspend and resume a port through the Set Port Feature (PORT_SUSPEND) and Clear Port Feature (PORT_SUSPEND). ...
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Hub Port Status Register The bits in this register are used by the microcontroller firmware when reporting a port's status through the Port Status Field, wPortStatus. Bits 3 (POCI) and 5 (PPSTAT) are used by the USB hardware and ...
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Bit 2 – PSSTAT: Port Suspend Status 0 = Port not suspended 1 = Port suspended Set and cleared by the hardware as controlled through Port Control Register. • Bit 1 – PESTAT: Port Enable Status 0 = Port ...
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Hub Port State Register – HPSTAT2...5 Bit Port2 $1FA9 Port3 $1FAA Port4 $1FAB Port5 $1FAC Read/Write Initial Value These registers contain the state of the ports’ DP and DM pins, which will be sent to the host upon receipt ...
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Reset complete This bit is set by the USB hardware after it completes RESET signaling which is initiated when the Reset and Enable Port command is detected at the Port Control Register, HPCON. The firm- ware sends this ...
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Hub and Port Power Management Overcurrent protection and power switching are required for the external downstream ports only. In the AT43USB325, these tasks are completely programmable. This means that any type of hub is achievable with the AT43USB325: self-powered ...
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Figure 8-1 hub design with global overcurrent protection and ganged power switching. Figure 8-1. Port Power Management BUS_POWER GND 3355C–USB–4/05 shows a simplified diagram of a power management circuit of an AT43USB325 based GND AT43USB325 OVCN PWRN FLG CTL IN ...
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Suspend and Resume The AT43USB325 enters suspend only when requested by the USB host through bus inactivity for at least 3 ms. The USB hardware would detect this request, sets the GLB_SUSP bit of SPRSR, Suspend/Resume Register, and interrupts ...
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Suspend and Resume Process 8.5.4.1 Global Suspend The Host stops sending packets, the hardware detects this as global suspend signaling and stops all downstream signaling. Finally, the hardware asserts the GLB_SUSP interrupt. 1. Host stops sending packets 2. Global ...
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Remote Wake-up, Downstream Ports The hardware detects a connect/disconnect/port resume and propagates resume signaling upstream. Finally, the hardware enables the oscillator and asserts the RSM interrupt. 1. Connect/disconnect/port resume detected 2. Propagate resume signaling 3. Enable Oscillator 4. Set ...
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Selective Suspend, Embedded Function 8.5.4.7 Selective Resume, Embedded Function 6. Send updated port status at next 3355C–USB–4/05 Hardware Hardware IN to endpoint1 AT43USB325 Firmware 1. Set Port Feature PORT_SUSPEND decoded 2. Disable Port 1’s endpoints 3. Set GPIO to ...
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Electrical Specification 9.1 Absolute Maximum Ratings Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated ...
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Table 9-4. Symbol V OL2 RPU V IL3 V IH3 V IL4 V IH4 V OL4 V OH4 C Note: Table 9-5. Symbol CX1 CX2 C12 Note: 9.2.1 AC Characteristics Table 9-6. Symbol ...
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Figure 9-1. Table 9-7. Symbol TR TF TRFM ZDRV Note: Figure 9-2. Table 9-8. Symbol TR TF TRFM AT43USB325 98 Synchronous Data Timing V IH SSN CSS SCK ...
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Figure 9-3. Table 9-9. USB Source Timings, Full-speed Operation Symbol Parameter (1) TDRATE Full Speed Data Rate (1) TFRAME Frame Interval TRFI Consecutive Frame Interval Jitter TRFIADJ Consecutive Frame Interval Jitter Source Diff Driver Jitter TDJ1 To Next Transition TDJ2 ...
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Figure 9-4. Figure 9-5. Figure 9-6. AT43USB325 100 Differential Data Jitter T PERIOD Crossover Differential Points Data Lines Consecutive Transitions N PERIOD XJR1 Paired Transitions N*T PERIOD Differential-to-EOP Transition Skew and EOP Width Crossover T Point PERIOD Extended ...
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Table 9-10. Symbol THDD2 THDJ1 THDJ2 TFSOP TFEOPD TFHESK Table 9-11. Symbol TLHDD TLHDJ1 TLHDJ2 TLUHJ1 TLUHJ2 TSOP TLEOPD TLHESK Table 9-12. Symbol TDCNN TDDIS TURSM TDRST TDSPDEV TURLK TURLSEO TURPSEO TUDEOP 3355C–USB–4/05 Hub Timings, Full-speed Operation Parameter Hub Differential ...
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Figure 9-7. Hub Differential Delay, Differential Jitter and SOP Distortion Upstream End of Cable V SS Differential Data Lines Downstream Hub Delay With Cable Figure 9-8. Hub EOP Delay and EOP Skew Upstream End of Cable V ...
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... Ordering Information 10.1 Standard Package Options Program Memory Ordering Code SRAM AT43USB325E-AC 10.2 Green Package Options (Pb/Halide-free/RoHS Compliant) Program Memory Ordering Code SRAM AT43USB325E-AU 64AA 64-lead, Low-profile (1.4 mm) Plastic Quad Flat Package (LQFP) 3355C–USB–4/05 Package 64AA LQFP Package 64AA LQFP ...
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Packaging Information 11.1 64AA – LQFP Dimensions in Millimeters and (Inches) Controlling Dimensions: Millimeters JEDEC STANDARD MS-026 ACB PIN 1 ID 0.50(0.020) BSC 0.20(0.008) 0.09(0.003) 2325 Orchard Parkway San Jose, CA 95131 R AT43USB325 104 PIN 1 10.10(0.397) 9.90(0.389) ...
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Errata Sheet Errata (All Date Codes): Missed Watchdog Timer Reset 12.1 Problem There is a synchronization problem between the watchdog clock and the AVR clock. Even though the clock inputs to both the watchdog timer and the AVR core ...
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Change Log Doc. Rev. 3355C 3355B AT43USB325 106 Comments • Change: Changes in the “Standard Package Options” on page 103 • Additions: Added numbering to document headings • Data Correction: timeout period data in • Additions: Addions to Table ...
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... Configuration .......................................................................................................2 1.2Pin Assignment .........................................................................................................3 1.3Signal Description .....................................................................................................4 3.1X-, Y- and Z- Registers ............................................................................................10 3.2Arithmetic Logic Unit (ALU) .....................................................................................10 3.3Program Memory .....................................................................................................10 3.4SPI Serial EEPROM Interface (AT43USB325E Only) .............................................11 3.5SRAM Data Memory ...............................................................................................12 3.6I/O Memory ..............................................................................................................17 3.7USB Hub .................................................................................................................18 4.1On-chip Power Supply .............................................................................................20 4.2I/O Pin Characteristics .............................................................................................20 4.3Oscillator and PLL ...................................................................................................20 4.4Reset and Interrupt Handling ..................................................................................21 4 ...
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Timer/Counters ...................................................................................... 42 7 I/O Ports .................................................................................................. 55 8 Programming the USB Module ............................................................. 63 9 Electrical Specification .......................................................................... 96 10 Ordering Information ........................................................................... 103 11 Packaging Information ........................................................................ 104 12 Errata Sheet .......................................................................................... 105 13 Change Log .......................................................................................... ...
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