AT43USB325E-AC Atmel, AT43USB325E-AC Datasheet - Page 54

• Manufacturer Part Number: AT43USB325E-AC
• Description: IC USB KEYBOARD CTRLR HUB 64LQFP
• Manufacturer: Atmel
• Series: AVR®r

Specifications of AT43USB325E-AC

• Applications: Keyboard Controller
• Core Processor: AVR
• Program Memory Type: SRAM (16 kB)
• Controller Series: AT43USB
• Ram Size: 512 x 8
• Interface: SPI, 3-Wire Serial
• Number Of I /o: 42
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.5.1
54
AT43USB325
Watch Dog Timer Control Register – WDTCR
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT43USB325 and will always read as zero.
• Bit 4 – WDTOE: Watch Dog Turn-Off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be dis-
abled. Once set, the hardware will clear this bit to zero after four clock cycles. Refer to the
description of the WDE bit for a watchdog disable procedure.
• Bit 3 – WDE: Watch Dog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the
Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To
disable an enabled watchdog timer, the following procedure must be followed:
• Bits 2..0 – WDP2, WDP1, WDP0: Watch Dog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Time-out Periods
are shown in
Table 6-8.
Note:
1. In the same operation, write a logical one to WDTOE and WDE. A logical one must be
2. Within the next four clock cycles, write a logical 0 to WDE. This disables the watchdog.
Read/Write
Initial Value
$21 ($41)
WDP2
Bit
0
0
0
0
1
1
1
1
written to WDE even though it is set to one before the disable operation starts.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog Timer is
enabled. This ensures that the reset period will be in accordance with the Watchdog Timer pres-
cale settings. If the Watchdog Timer is enabled without reset, the watchdog timer may not start to
count from zero. To avoid unintentional MCU reset, the Watchdog Timer should be disabled or
reset before changing the Watchdog Timer Prescale Select.
Table
WDP1
Watchdog Timer Prescale Select
R
7
–
0
0
0
1
1
0
0
1
1
6-8.
R
6
–
0
WDP0
0
1
0
1
0
1
0
1
R
5
–
0
Number of WDT Oscillator cycles
8K cycles
16K cycles
32K cycles
64K cycles
128K cycles
256K cycles
512K cycles
1,024K cycles
WDTOE
R/W
4
0
WDE
R/W
3
0
WDP2
R/W
2
0
WDP1
R/W
1
0
WDP0
Time-out
8.2 ms
16.4 ms
33.8 ms
65.6 ms
0.131 s
0.262 s
0.524 s
1.048 s
R/W
0
0
3355C–USB–4/05
WDTCR