AT43USB325E-AC Atmel, AT43USB325E-AC Datasheet - Page 77

• Manufacturer Part Number: AT43USB325E-AC
• Description: IC USB KEYBOARD CTRLR HUB 64LQFP
• Manufacturer: Atmel
• Series: AVR®r

Specifications of AT43USB325E-AC

• Applications: Keyboard Controller
• Core Processor: AVR
• Program Memory Type: SRAM (16 kB)
• Controller Series: AT43USB
• Ram Size: 512 x 8
• Interface: SPI, 3-Wire Serial
• Number Of I /o: 42
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.3.10
8.3.11
3355C–USB–4/05
Hub Endpoint 0 Control and Acknowledge Register – HCAR0
Function Endpoint 0 Control and Acknowledge Register – FCAR0
• Bit 7 – DIR: Control transfer direction
It is set by the microcontroller firmware to indicate the direction of a control transfer to the USB
hardware. The FW writes to this bit location after it receives an RX SETUP interrupt. The hard-
ware uses this bit to determine the status phase of a control transfer.
0 = control write or no data stage
1 = control read
• Bit 6 – DATA END
When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last
data packet in FIFO, or that the microcontroller has processed the last data packet it expects
from the Host. This bit is used by control endpoints only together with bit 4 (TX Packet Ready) to
signal the USB hardware to go to the STATUS phase after the packet currently residing in the
FIFO is transmitted. After the hardware completes the STATUS phase it will interrupt the micro-
controller without clearing this bit.
• Bit 5 – FORCE STALL
This bit is set by the microcontroller to indicate a stalled endpoint. The hardware will send a
STALL handshake as a response to the next IN or OUT token, or whenever there is a control
transfer without a Data Stage.
The microcontroller sets this bit if it wants to force a STALL. A STALL is sent if any of the follow-
ing condition is encountered:
• Bit 4 – TX PACKET READY: Transmit Packet Ready
When set by the firmware, this bit indicates that the microcontroller has loaded the FIFO with a
packet of data. This bit is cleared by the hardware after the USB Host acknowledges the packet.
For ISO endpoints, this bit is cleared unconditionally after the data is sent.
This bit is used for the following operations:
Initial Value
Read/Write
1. An unsupported request is received.
2. The host continues to ask for data after the data is exhausted.
3. The control transfer has no data stage.
1. Control read transactions by a control endpoint.
2. IN transactions with DATA1 PID to complete the status phase for a control endpoint,
3. By a BULK IN or ISO IN or INT IN endpoint.
Hub EP0
Function
$1FDD
$1FA7
EP0
Bit
when this bit is zero but Data End set high (bit 4).
R/W
DIR
DIR
7
0
DATA
DATA
END
END
R/W
6
0
FORCE
FORCE
STALL
STALL
R/W
5
0
PACKET
PACKET
READY
READY
R/W
TX
TX
4
0
STALL_
STALL_
SENT_
SENT_
ACK
ACK
R/W
3
0
SETUP_
SETUP_
ACK
ACK
RX_
RX_
R/W
2
0
RX_OUT_
PACKET_
RX_OUT_
PACKET_
ACK
ACK
R/W
1
0
AT43USB325
COMPLETE_
COMPLETE_
ACK
ACK
R/W
TX_
TX_
0
0
FCAR
HCA
R0
0
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