AT43USB325E-AC Atmel, AT43USB325E-AC Datasheet - Page 27

• Manufacturer Part Number: AT43USB325E-AC
• Description: IC USB KEYBOARD CTRLR HUB 64LQFP
• Manufacturer: Atmel
• Series: AVR®r

Specifications of AT43USB325E-AC

• Applications: Keyboard Controller
• Core Processor: AVR
• Program Memory Type: SRAM (16 kB)
• Controller Series: AT43USB
• Ram Size: 512 x 8
• Interface: SPI, 3-Wire Serial
• Number Of I /o: 42
• Voltage - Supply: 4.4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.9.2
4.9.3
3355C–USB–4/05
General Interrupt Flag Register – GIFR
Timer/Counter Interrupt Mask Register – TIMSK
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT43USB325 and always read as zero.
• Bit 7 – INTF1: External Interrupt Flag1
When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-
bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at
address $004. The flag is cleared when the interrupt routine is executed. Alternatively, the flag
can be cleared by writing a logical one to it.
• Bit 6 – INTF0: Interrupt Flag0 (Suspend/Resume Interrupt Flag)
When an event on the INT0 (that is, a USB event-related interrupt) triggers an interrupt request,
INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU
will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is
executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT43USB325 and always read as zero.
• Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is
executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is set in the
Timer/Counter Interrupt Flag Register (TIFR).
• Bit 6 – OCE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector
$004) is executed if a CompareA match in Timer/Counter1 occurs, i.e., when the OCF1A bit is
set in the TIFR.
• Bit 5 – OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector
Read/Write
Initial Value
Read/Write
Initial Value
$3A ($5A)
$39 ($59)
Bit
Bit
TOIE1
R/W
INTF1
R/W
7
0
7
0
OCIE1A
R/W
6
0
INT F0
R/W
6
0
OCIE1NB
R/W
5
0
R
5
–
0
4
–
R
0
R
4
–
0
TICIE1
R/W
3
0
R
3
–
0
R
2
–
0
R
0
2
–
AT43USB325
TOIE0
R/W
1
0
R
1
–
0
R
0
–
0
R
0
–
0
TIMSK
GIFR
27