MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 21

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.3.6.4
1.3.7
The PCI interface on the MPC5200B is designed to PCI Version 2.2 and supports 33 MHz and 66 MHz PCI operations. See the
PCI Local Bus Specification; the component section specifies the electrical and timing parameters for PCI components with the
intent that components connect directly together whether on the planar or an expansion board, without any external buffers or
other “glue logic.” Parameters apply at the package pins, not at expansion board edge connectors.
The MPC5200B is always the source of the PCI CLK. The clock waveform must be delivered to each 33 MHz or 66 MHz PCI
component in the system.
environments.
Freescale Semiconductor
data
t
data
mem_clk
t
MDQS (Data Strobe)
Sym
DQSS
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1, and CLK_EN
valid
hold
Control Signals
PCI
Table 22
MDQ (Data)
Memory Interface Timing-DDR SDRAM Write Command
MEM_CLK
MEM_CLK
Delay from write command to first
MDQ valid before rising edge of
MDQ valid after rising edge of
summarizes the clock specifications.
rising edge of MDQS
MEM_CLK period
Figure 9
Description
Write
MDQS
MDQS
t
DQSS
shows the clock waveform and required measurement points for 3.3 V signaling
Table 21. DDR SDRAM Memory Write Timing
Figure 8. DDR SDRAM Memory Write Timing
datavalid
datahold
MPC5200B Data Sheet, Rev. 4
Write
Min
7.5
1.0
1.0
—
Write
t
mem_clk
Max
—
—
—
Write
+ 0.4
Units
ns
ns
ns
ns
SpecID
A5.20
A5.21
A5.22
A5.23
21