IC MPU 32BIT 400MHZ 272-PBGA

MPC5200CVR400B

Manufacturer Part NumberMPC5200CVR400B
DescriptionIC MPU 32BIT 400MHZ 272-PBGA
ManufacturerFreescale Semiconductor
MPC5200CVR400B datasheets
 


Specifications of MPC5200CVR400B

Processor TypeMPC52xx PowerPC 32-BitSpeed400MHz
Voltage1.5VMounting TypeSurface Mount
Package / Case272-PBGAProcessor SeriesMPC52xx
Coree300Development Tools By SupplierMEDIA5200KIT1E
Maximum Clock Frequency400 MHzMaximum Operating Temperature+ 105 C
Mounting StyleSMD/SMTI/o Voltage2.5 V, 3.3 V
Minimum Operating Temperature- 40 CCore Size32 Bit
No. Of I/o's56Ram Memory Size16KB
Cpu Speed400MHzNo. Of Timers8
Embedded Interface TypeCAN, I2C, SCI, SPINo. Of Pwm Channels8
Digital Ic Case StyleTEPBGARohs CompliantYes
Lead Free Status / RoHS StatusLead free / RoHS CompliantFeatures-
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Freescale Semiconductor
Data Sheet
MPC5200 Data Sheet
NOTE
The information in this
document is subject to
change. For the latest data
on the MPC5200, visit
www.freescale.com and
proceed to the MPC5200
Product Summary Page.
1
Overview
The MPC5200 integrates a high performance MPC603e
series G2_LE core with a rich set of peripheral functions
focused on communications and systems integration.
The G2_LE core design is based on the PowerPC
architecture. MPC5200 incorporates an innovative
BestComm I/O subsystem, which isolates routine
maintenance of peripheral functions from the embedded
G2_LE core. The MPC5200 contains a SDRAM/DDR
Memory Controller, a flexible External Bus Interface,
PCI Controller, USB, ATA, Ethernet, six Programmable
2
Serial Controllers (PSC), I
C, SPI, CAN, J1850, Timers,
and GPIOs.
“Definitive Data: Freescale reserves the right to change the production detail specifications
as may be required to permit improvements in the design of its products.”
© Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Table of Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3
Electrical and Thermal Characteristics . . . . . . . . . 6
3.1 DC Electrical Characteristics . . . . . . . . . . . . . 6
3.2 Oscillator and PLL Electrical
Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 AC Electrical Characteristics . . . . . . . . . . . . 14
4
Package Description . . . . . . . . . . . . . . . . . . . . . . 64
4.1 Package Parameters . . . . . . . . . . . . . . . . . . 64
4.2 Mechanical Dimensions. . . . . . . . . . . . . . . . 64
4.3 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . 66
5
System Design Information. . . . . . . . . . . . . . . . . 71
5.1 Power UP/Down Sequencing . . . . . . . . . . . 71
5.2 System and CPU Core AVDD power
supply filtering . . . . . . . . . . . . . . . . . . . . . . . 73
5.3 Pull-up/Pull-down Resistor Requirements . . 73
5.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
TM
core
6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 79
7
Document Revision History. . . . . . . . . . . . . . . . . 79
MPC5200
Rev. 4, 01/2005

MPC5200CVR400B Summary of contents

  • Page 1

    ... Serial Controllers (PSC SPI, CAN, J1850, Timers, and GPIOs. “Definitive Data: Freescale reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.” © Freescale Semiconductor, Inc., 2005, 2006. All rights reserved. Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Features ...

  • Page 2

    ... BestComm DMA subsystem — Intelligent virtual DMA Controller — Dedicated DMA channels to control peripheral reception and transmission — Local memory (SRAM 16 kBytes) • 6 Programmable Serial Controllers (PSC), configurable for the following: — UART or RS232 interface MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor ...

  • Page 3

    ... Systems Protection (watch dog timer, bus monitor) — Individual control of functional block clock sources — Power management: Nap, Doze, Sleep, Deep Sleep modes — Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN) Freescale Semiconductor 2 C) MPC5200 Data Sheet, Rev. 4 ...

  • Page 4

    ... Features • Test/Debug features — JTAG (IEEE 1149.1 test access port) — Common On-chip Processor (COP) debug port • On-board PLL and clock generation Figure 1 shows a simplified MPC5200 block diagram. 4 MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor ...

  • Page 5

    ... Figure 1. Simplified Block Diagram—MPC5200 Freescale Semiconductor BestComm DMA SRAM 16K MPC5200 Data Sheet, Rev. 4 Features MSCAN 2x J1850 USB 2x SPI Ethernet PSC 6x 5 ...

  • Page 6

    ... D1.4 –0.3 VDD_IO + 0.3 V D1.5 –0.3 VDD_MEM_IO V D1.6 + 0.3 – 1.0 V D1.7 – 1.0 V D1.8 o –55 150 C D1.9 1 (1) Max Unit 1.58 V 3.6 V 3.6 V 2.63 V 1.58 V 1.58 V VDD_IO V VDD_MEM_IO V SDR Freescale Semiconductor SpecID D2.1 D2.2 D2.3 D2.4 D2.5 D2.6 D2.7 D2.8 ...

  • Page 7

    ... Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Freescale Semiconductor Symbol Min Vin DDR Aext Tj Tjext Table 3 ...

  • Page 8

    ... SpecID µA — +10 D3.13 µA — +10 D3.14 µA — +10 D3.15 µA 40 109 D3.16 µA 41 111 D3.17 µA 36 106 D3.18 2.4 — V D3.19 1.7 — V D3.20 — 0.4 V D3.21 — 0.4 V D3.22 -1.0 1.0 mA D3.23 — D3.24 I Unit SpecID D3. D3.26 Freescale Semiconductor ...

  • Page 9

    ... SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO). figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated by the user for each application case using the following formula Freescale Semiconductor ...

  • Page 10

    ... P total = P core + P analog + P IO Table 6. Power Dissipation Core Power Supply (VDD_CORE) 33/132/66/132/396 Typ 1080 600 225 225 52.5 Typ 2 Typ 33 MPC5200 Data Sheet, Rev. 4 SpecID Unit Notes D5.5 Unit Notes Unit Notes 9 mW D5 SDR Freescale Semiconductor ...

  • Page 11

    ... The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Freescale Semiconductor Table 7. Thermal Resistance Data Value R θ ...

  • Page 12

    ... For instance, the user can change the air flow around θCA 1-3 . The junction to case covers the situation where a heat sink will be ) can be used to determine the junction temperature with a JT × +(Ψ MPC5200 Data Sheet, Rev. 4 Eqn. 2 Eqn. 3 Freescale Semiconductor ...

  • Page 13

    ... Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for the PLL lock after a stable Vdd and core_sysclk are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes. Freescale Semiconductor Symbol Notes ...

  • Page 14

    ... GPIOs and Timers • IEEE 1149.1 (JTAG) AC Specifications MPC5200 Data Sheet, Rev. 4 Max Unit SpecID — 550 MHz O4.1 — 40.0 ns O4.2 — 1200 MHz O4.3 — 367 MHz O4.4 — 50.0 ns O4.5 — 150 ps O4.6 µs — 100 O4.7 Freescale Semiconductor ...

  • Page 15

    ... MPC5200. 1 G2_LE Processor Core 2 SDRAM Clock 3 XL Bus Clock 4 IP Bus Clock 5 PCI / Local Plus Bus Clock 6 PLL Input Range 3.3.2 Clock AC Specifications t DUTY V SYSCLK M Freescale Semiconductor Table 12. Clock Frequencies Min — — — — — 15.6 t CYCLE t t DUTY RISE Figure 2. Timing Diagram— ...

  • Page 16

    ... NOTE MPC5200 Data Sheet, Rev. 4 Min Max Units SpecID 28.6 64.1 ns A2.1 — 5.0 ns A2.2 — 5.0 ns A2.3 40.0 60.0 % A2.4 2.0 — V A2.5 — 0.8 V A2.6 Reference Clock SpecID SYS_XTAL_IN A3.1 SYS_XTAL_IN A3.2 SYS_XTAL_IN A3.3 Freescale Semiconductor ...

  • Page 17

    ... PORRESET) are inactive (high), the contents of this register get locked after two further SYS_XTAL cycles (see Figure 3). SYS_XTAL PORRESET HRESET RST_CFG_WRD sample sample Figure 3. Reset Configuration Word Locking Freescale Semiconductor Table 15. Reset Rise / Fall Timing Min — — — — — — NOTE NOTE ...

  • Page 18

    ... IRQ0 10 IRQ1 10 IRQ2 10 10 IRQ3 MPC5200 Data Sheet, Rev. 4 Encoder core_cint core_int G2_LE Core Grouper Encoder Core Interrupt IP_CLK critical (cint) IP_CLK normal (int) IP_CLK normal (int) IP_CLK normal (int) IP_CLK normal (int) Freescale Semiconductor SpecID A4.1 A4.2 A4.3 A4.5 A4.6 ...

  • Page 19

    ... XL bus, and IP bus frequencies (depending on board design and programming). In addition advisable to execute an interrupt handler, which has been implemented in assembly code. Freescale Semiconductor Pin Name Clock Cycles Reference Clock ...

  • Page 20

    ... READ NOP DM DM valid hold data setup t hold Column t hold MPC5200 Data Sheet, Rev. 4 Max Units — *0.5+0.4 ns mem_clk — *0.25+0.4 ns mem_clk — ns 0.3 ns — ns NOP NOP NOP NOP data hold Freescale Semiconductor SpecID A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 A5.7 ...

  • Page 21

    ... CDM Reset Configuration Register tap delay bits. Note: These bits in the CDM Reset Configuration register are not ‘reset configured’ but have a hard coded reset value and are writable during operation. Freescale Semiconductor Table 19. Standard SDRAM Write Timing Min 7.5 — ...

  • Page 22

    ... Calculated with maximum number of Tap delay, 31 Tap delay are selected. 2 Calculated with minimum number of Tap delay, 0 Tap delay are selected. 22 Min 7.5 — t *0.5 mem_clk — 2 1.55 MPC5200 Data Sheet, Rev. 4 Max Units SpecID — ns A5.15 t *0.5+0.4 ns A5.16 mem_clk — ns A5.17 1 4.59 ns A5.18 — ns A5.19 Freescale Semiconductor ...

  • Page 23

    ... Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the vaild MDQS signal NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN Figure 7. Timing Diagram—DDR SDRAM Memory Read Timing Freescale Semiconductor t hold ...

  • Page 24

    ... A. With a longer connection maybe two sample shows a example with two working sample position (A and B). With a MPC5200 Data Sheet, Rev. 4 Possible sample time over PVT for one selected Tap delay Working Tap Delay range for sample position A 31 selected Tap delay Tap delay number Freescale Semiconductor ...

  • Page 25

    ... Parameters apply at the package pins, not at expansion board edge connectors. The MPC5200 is always the source of the PCI CLK. The clock waveform must be delivered to each 33-MHz or 66-MHz PCI component in the system. measurement points for 3.3 V signaling environments. Freescale Semiconductor Min 7.5 — Write ...

  • Page 26

    ... The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter cyc T T high low 0.6Vcc 0.2Vcc Figure 10. PCI CLK Waveform Table 22. PCI CLK Specifications 66 MHz 33 MHz Min Max Min 1 Figure 10. MPC5200 Data Sheet, Rev. 4 0.4Vcc, p-to-p (minimum) Units Notes SpecID Max ns 1,3 A6.1 ns A6.2 A6.3 4 V/ns 2 A6.4 Freescale Semiconductor ...

  • Page 27

    ... REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup MHz. All other signals are bused. 4. See the timing measurement conditions in the PCI Local Bus Specification [4]. For Measurement and Test Conditions, see the PCI Local Bus Specification [4]. Freescale Semiconductor Table 23. PCI Timing Parameters 66 MHz 33 MHz ...

  • Page 28

    ... PCIck t IPBIck t IPBIck t IPBIck 2.8 0 (DC+1)*t t PCIck - MPC5200 Data Sheet, Rev. 4 Max Units Notes SpecID 1.8 ns A7.1 1 A7.3 PCIck t ns A7.4 PCIck - ns 2 A7.5 0.4 ns A7.6 0 A7. A7. A7.12 ns A7.13 PCIck - ns 3 A7. A7.15 PCIck Freescale Semiconductor ...

  • Page 29

    ... ACK is input and can be used to shorten the CS pulse width. 4. Only available in Large Flash and MOST Graphics mode. 5. Only available in MOST Graphics mode. CS[x] t2 ADDR OE t6 R/W DATA (wr) DATA (rd) ACK t14 TS TSIZ[1:2] Figure 12. Timing Diagram—Non-MUXed Mode Freescale Semiconductor Min - t PCIck t IPBIck t IPBIck t10 t12 t15 t16 MPC5200 Data Sheet, Rev ...

  • Page 30

    ... MPC5200 Data Sheet, Rev. 4 Max Units Notes SpecID 1.8 ns A7.20 1.8 ns A7.21 LB *2*(32/DS)) ns 1,2 A7.22 PCIck ns A7.23 PCIck -0.7 ns A7.24 0.4 ns A7.25 0.4 ns A7. A7. A7. A7. A7.30 ns A7.31 PCIck ns A7.32 PCIck 0 A7.33 ns 2,3 A7.34 PCIck 0.8 ns A7.35 ns A7.36 PCIck Freescale Semiconductor ...

  • Page 31

    ... PCI CLK CS[x] t2 ADDR OE t6 R/W DATA (rd) ACK TS Freescale Semiconductor t1 t4 t11 t13 t14 t15 Figure 13. Timing Diagram—Burst Mode MPC5200 Data Sheet, Rev. 4 Electrical and Thermal Characteristics t10 t9 t12 31 ...

  • Page 32

    ... PCIck - 0 PCIck (2+WS)*t (2+WS)*t PCIck - 0.4 - 0.4 t IPBIck - t PCIck t IPBIck - t PCIck MPC5200 Data Sheet, Rev. 4 Units Notes SpecID ns A7.15 ns A7.16 ns A7.16 ns A7.17 ns A7.18 ns A7. A7. A7. A7.22 PCIck ns A7.23 ns A7.24 ns A7.24 ns A7.25 PCIck ns A7.26 ns A7. A7.26 ns A7. A7. A7.28 Freescale Semiconductor ...

  • Page 33

    ... ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification [5] and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5200 User Manual [1]. Freescale Semiconductor t2 t1 ...

  • Page 34

    ... MPC5200 Data Sheet, Rev. 4 Mode 2 Mode 3 Mode 4 SpecID (ns) (ns) (ns) 240 180 120 A8 A8.2 100 80 70 A8.3 290 80 70 — A8.10 1250 1250 1250 A8.11 Freescale Semiconductor ...

  • Page 35

    ... DIOW data hold tI DMACK to DIOR/DIOW setup tJ DIOR/DIOW to DMACK hold tKr DIOR negated pulse width tKw DIOW negated pulse width tLr DIOR to DMARQ delay tLw DIOW to DMARQ delay Freescale Semiconductor Figure 15. PIO Mode Timing Min/Max Mode 0(ns) min 480 max — min ...

  • Page 36

    ... Data valid hold time at sender, from STROBE edge. 200 0 170 First STROBE time for drive to first negate DSTROBE from STOP during a data-in burst. MPC5200 Data Sheet, Rev Comment SpecID A8.26 A8.27 A8.28 A8.29 A8.30 A8.31 A8.32 A8.33 Freescale Semiconductor ...

  • Page 37

    ... Even though the sender stops generating STROBE edges, the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at 1.5 V. Freescale Semiconductor MODE 2 (ns) ...

  • Page 38

    ... DSTROBE at host t DD(0:15) at host Figure 18. Timing Diagram—Sustained Ultra DMA Data In Burst ACK ENV t ZAD t t ACK ENV t ZAD t ZIORDY ACK t 2CYC t t CYC CYC t t DVS DVH MPC5200 Data Sheet, Rev DVS DVH t 2CYC t t DVS DVH t DH Freescale Semiconductor ...

  • Page 39

    ... DD[0:15] (device) Figure 19. Timing Diagram—Host Pausing an Ultra DMA Data In Burst DMARQ (device) DMACK (host) STOP (host) HDMARDY (host DSTROBE (device) DD[0:15] DA0,DA1,DA2, CS[0:1] Figure 20. Timing Diagram—Drive Terminating Ultra DMA Data In Burst Freescale Semiconductor RFS MLI ZAH t DVS t AZ MPC5200 Data Sheet, Rev ...

  • Page 40

    ... Electrical and Thermal Characteristics DMARQ (device) DMACK (host) t STOP (host) HDMARDY (host) t RFS DSTROBE (device) DD[0:15] DA0,DA1,DA2, CS[0:1] Figure 21. Timing Diagram—Host Terminating Ultra DMA Data In Burst ZAH MPC5200 Data Sheet, Rev MLI t ACK t ACK t MLI t IORDYZ t DVS t DVH CRC t ACK Freescale Semiconductor ...

  • Page 41

    ... DD[0:15] (host) DA0,DA1,DA2, CS[0:1] Figure 22. Timing Diagram—Initiating an Ultra DMA Data Out Burst HSTROBE (host) t DVH DD[0:15] (host) HSTROBE (device DD[0:15] (device) Figure 23. Timing Diagram—Sustained Ultra DMA Data Out Burst Freescale Semiconductor ENV t ACK ZIORDY t ACK t ACK t 2CYC t t CYC ...

  • Page 42

    ... Figure 24. Timing Diagram—Drive Pausing an Ultra DMA Data Out Burst DMARQ (device) DMACK (host STOP (host) DDMARDY (device) HSTROBE (host) DD[0:15] (host) DA0,DA1,DA2, CS[0:1] Figure 25. Timing Diagram—Host Terminating Ultra DMA Data Out Burst RFS MLI DVS MPC5200 Data Sheet, Rev ACK t IORDYZ t ACK t DVH CRC t ACK Freescale Semiconductor ...

  • Page 43

    ... DD[0:15] (host) DA0,DA1,DA2, CS[0:1] Figure 26. Timing Diagram—Drive Terminating Ultra DMA Data Out Burst Sym Description 1 ata_isolation setup time 2 ata_isolation hold time DIOR ATA_ISOLATION Freescale Semiconductor RFS LI Table 30. Timing Specification ata_isolation 1 Figure 27. Timing Diagram-ATA-ISOLATION MPC5200 Data Sheet, Rev. 4 Electrical and Thermal Characteristics ...

  • Page 44

    ... RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification [6]. RX_CLK (Input) RXD[3:0] (inputs) RX_DV RX_ER Figure 28. Ethernet Timing Diagram—MII Rx Signal 44 Table 31. MII Rx Signal Timing Min Max 10 — 10 — 35% 65% 35% 65 MPC5200 Data Sheet, Rev. 4 Unit SpecID ns A9.1 ns A9.2 1 RX_CLK Period A9.3 1 RX_CLK Period A9.4 Freescale Semiconductor ...

  • Page 45

    ... MHz. See the IEEE 802.3 Specification [6]. TX_CLK (Input) TXD[3:0] (Outputs) TX_EN TX_ER Figure 29. Ethernet Timing Diagram—MII Tx Signal Sym Description M8 CRS, COL minimum pulse width Figure 30. Ethernet Timing Diagram—MII Async Freescale Semiconductor Table 32. MII Tx Signal Timing Min 0 35% 35 Table 33. MII Async Signal Timing Min 1 ...

  • Page 46

    ... M14 M9 M10 M11 Description MPC5200 Data Sheet, Rev. 4 Max Unit SpecID 25 ns — ns — ns — ns — ns — ns Min Max Units SpecID 83.3 667 ns 83.3 667 ns — 7.9 ns — 7.9 ns Freescale Semiconductor A9.9 A9.10 A9.11 A9.12 A9.13 A9.14 A10.1 A10.2 A10.3 A10.4 ...

  • Page 47

    ... Slave disable lag time 8 Sequential transfer delay 9 Clock falling time 10 Clock rising time 11 NOTES: 1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. Output timing was specified at a nominal 50 pF load. Freescale Semiconductor NOTE Description NOTE MPC5200 Data Sheet, Rev. 4 Electrical and Thermal Characteristics Min ...

  • Page 48

    ... NOTE MPC5200 Data Sheet, Rev Max Units SpecID 1 1024 IP-Bus Cycle A11.12 1 512 IP-Bus Cycle A11.13 — ns A11.14 50.0 ns A11.15 50.0 ns A11.16 — ns A11.17 — ns A11.18 — ns A11.19 1 — IP-Bus Cycle A11.20 Freescale Semiconductor ...

  • Page 49

    ... Slave disable lag time 8 Sequential Transfer delay 9 Clock falling time 10 Clock rising time NOTES: 1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. Output timing was specified at a nominal 50 pF load. Freescale Semiconductor Description NOTE MPC5200 Data Sheet, Rev. 4 Electrical and Thermal Characteristics 9 ...

  • Page 50

    ... Description NOTE MPC5200 Data Sheet, Rev Min Max Units SpecID 1 4 1024 IP-Bus Cycle A11. 512 IP-Bus Cycle A11.32 15.0 — ns A11.33 — 50.0 ns A11.34 50.0 — ns A11.35 0.0 — ns A11.36 15.0 — ns A11. — IP-Bus Cycle A11.38 Freescale Semiconductor ...

  • Page 51

    ... Data setup time 8 Start condition setup time (for repeated start condition only) 9 Stop condition setup time NOTES: 1 Inter Peripheral Clock is defined in the MPC5200 User Manual [1]. Freescale Semiconductor Input Timing Specifications—SCL and SDA Description MPC5200 Data Sheet, Rev. 4 Electrical and Thermal Characteristics ...

  • Page 52

    ... Min Max Units SpecID 3 6 — IP-Bus Cycle A13 — IP-Bus Cycle A13.9 — 7.9 ns A13. — IP-Bus Cycle A13.11 — 7.9 ns A13. — IP-Bus Cycle A13. — IP-Bus Cycle A13. — IP-Bus Cycle A13. — IP-Bus Cycle A13. Freescale Semiconductor ...

  • Page 53

    ... FrameSync valid after clock edge 6 FrameSync invalid after clock edge 7 Output Data valid after clock edge 8 Input Data setup time NOTES: 1 Bit Clock cycle time Output timing was specified at a nominal 50 pF load. Freescale Semiconductor 2 S Mode Min 40.0 — — — — — — ...

  • Page 54

    ... Min 40.0 1.0 1.0 1.0 NOTE MPC5200 Data Sheet, Rev Master Mode 2 S Slave Mode Typ Max Units — — — 50 — % — — ns — — 14.0 ns — — ns — — ns Freescale Semiconductor SpecID A15.9 A15.10 A15.11 A15.12 A15.13 A15.14 ...

  • Page 55

    ... Clock pulse low time 4 Frame valid after rising clock edge 5 Output Data valid after rising clock edge 6 Input Data setup time 7 Input Data hold time Output timing was specified at a nominal 50 pF load. Freescale Semiconductor Min 1.0 1.0 NOTE MPC5200 Data Sheet, Rev. 4 ...

  • Page 56

    ... FIR / MIR) Figure 41. Timing Diagram — IrDA Transmit Line Figure 40. Timing Diagram — AC97 Mode Description NOTE MPC5200 Data Sheet, Rev. 4 Min Max Units SpecID µs 0.125 10000 A15.22 µs 0.125 10000 A15.23 — 7.9 ns A15.24 — 7.9 ns A15.25 Freescale Semiconductor ...

  • Page 57

    ... Output timing was specified at a nominal 50 pF load. SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 4 MOSI Output 6 MISO Input Figure 42. Timing Diagram — SPI Master Mode, Format 0 (CPHA = 0) Freescale Semiconductor Description NOTE MPC5200 Data Sheet, Rev. 4 Electrical and Thermal Characteristics Min ...

  • Page 58

    ... Figure 43. Timing Diagram — SPI Slave Mode, Format 0 (CPHA = 0) 58 Description NOTE MPC5200 Data Sheet, Rev. 4 Min Max Units SpecID 30.0 — ns A15.37 15.0 — ns A15.38 1.0 — ns A15.39 1.0 — ns A15.40 1.0 — ns A15.41 — 14.0 ns A15.42 — 14.0 ns A15.43 0.0 — ns A15.44 30.0 — — A15. Freescale Semiconductor ...

  • Page 59

    ... Output timing was specified at a nominal 50 pF load. SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 4 MOSI Output MISO Input Figure 44. Timing Diagram — SPI Master Mode, Format 1 (CPHA = 1) Freescale Semiconductor Description NOTE MPC5200 Data Sheet, Rev. 4 Electrical and Thermal Characteristics Min Max ...

  • Page 60

    ... Figure 45. Timing Diagram — SPI Slave Mode, Format 1 (CPHA = 1) 60 Description NOTE MPC5200 Data Sheet, Rev. 4 Min Max Units SpecID 30.0 — ns A15.56 15.0 — ns A15.57 0.0 — ns A15.58 — 14.0 ns A15.59 2.0 — ns A15.60 1.0 — ns A15.61 0.0 — ns A15.62 30.0 — ns A15. Freescale Semiconductor ...

  • Page 61

    ... Clock Period CK t Input Setup for Async Signal IS t Input Hold for Async Signals IH t Output Valid DV t Output Hold DH Output Input Figure 46. Timing Diagram—Asynchronous Signals Freescale Semiconductor Table 50 gives the timing specifications. Table 50. Asynchronous Signals Description valid valid MPC5200 Data Sheet, Rev. 4 ...

  • Page 62

    ... VM = Midpoint Voltage Numbers shown reference MPC5200 Data Sheet, Rev. 4 Min Max Unit SpecID 0 25 MHz A17.1 40 — ns A17.2 1.08 — ns A17 A17.4 10 — ns A17.5 5 — ns A17.6 5 — ns A17.7 15 — ns A17 A17 A17.10 5 — ns A17.11 1 — ns A17. A17. A17. Table 51. Freescale Semiconductor ...

  • Page 63

    ... TCK DATA INPUTS DATA OUTPUTS DATA OUTPUTS Figure 49. Timing Diagram—JTAG Boundary Scan TCK TDI, TMS TDO TDO Figure 50. Timing Diagram—Test Access Port Freescale Semiconductor 4 5 Figure 48. Timing Diagram—JTAG TRST MPC5200 Data Sheet, Rev. 4 Electrical and Thermal Characteristics Numbers shown reference Table 51 ...

  • Page 64

    ... The MPC5200 uses TE-PBGA package. The package parameters are as provided in the following list: • Package outline • Interconnects 272 • Pitch 1.27 mm 4.2 Mechanical Dimensions Figure 51 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200, 272 TE-PBGA package. 64 MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor ...

  • Page 65

    ... PIN A1 INDEX 0 TOP VIEW e 19X (E1 BOTTOM VIEW Figure 51. Mechanical Dimensions and Pinout Assignments for the MPC5200, 272 TE-PBGA Freescale Semiconductor D C 0 0.2 M (D1) e 19X 272X A 0 0.15 M CASE 1135A–01 ISSUE B MPC5200 Data Sheet, Rev. 4 Package Description A 272X NOTES: 1 ...

  • Page 66

    ... TTL TTL TTL TTL TTL PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI DRV8 TTL DRV8 TTL PCI PCI PCI PCI PCI PCI DRV8 TTL PCI PCI PCI PCI PCI PCI Freescale Semiconductor ...

  • Page 67

    ... ETH_2 USB_TXP, TX, TXD[1] ETH_3 USB_PRTPWR, TXD[2] ETH_4 USB_SPEED, TXD[3] ETH_5 USB_SUPEND, TX_ER ETH_6 USB_OE, RTS, MDC ETH_7 TXN, MDIO Freescale Semiconductor Output Driver Type Power Supply Type I/O VDD_IO PCI Local Plus I/O VDD_IO DRV8 I/O VDD_IO DRV8 I/O VDD_IO DRV8 ...

  • Page 68

    ... DRV4 I/O VDD_IO DRV4 MPC5200 Data Sheet, Rev. 4 Input Pull-up/ Type down TTL Schmitt TTL Schmitt TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Schmitt Schmitt Schmitt Freescale Semiconductor ...

  • Page 69

    ... USB_RXP, CD PSC3_5 USB_RXN PSC3_6 USB_PRTPWR, Mclk, MOSI PSC3_7 USB_SPEED. MISO PSC3_8 USB_SUPEND, SS PSC3_9 USB_OVRCNT, SCK GPIO_WKUP_6 MEM_CS1 GPIO_WKUP_7 TIMER_0 Freescale Semiconductor Output Driver Type Power Supply Type I/O VDD_IO DRV4 PSC I/O VDD_IO DRV4 I/O VDD_IO DRV4 I/O VDD_IO DRV4 I/O ...

  • Page 70

    ... VDD_IO DRV4 MPC5200 Data Sheet, Rev. 4 Input Pull-up/ Type down TTL TTL TTL TTL TTL TTL TTL Schmitt 1 Schmitt 1 Schmitt TTL TTL TTL TTL TTL TTL TTL TTL PULLUP TTL TTL PULLUP TTL PULLUP TTL TTL PULLUP TTL PULLUP Freescale Semiconductor ...

  • Page 71

    ... MPC5200 I/O power rail if the external signal is driven above the MPC5200 I/O power rail voltage. 5 System Design Information 5.1 Power UP/Down Sequencing Figure 52 shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL VDD (PLL_AVDD), and Core VDD (VDD_CORE). Freescale Semiconductor Output Driver Type Power Supply Type Power and Ground - - ...

  • Page 72

    ... ESD protection clamp diodes. The recommended power up sequence is as follows: Use one microsecond or slower rise time for all supplies. 72 Figure 52. Supply Voltage Sequencing MPC5200 Data Sheet, Rev. 4 VDD_IO, VDD_IO_MEM (SDR) VDD_IO_MEM (DDR) VDD_CORE, PLL_AVDD Time Freescale Semiconductor ...

  • Page 73

    ... The MPC5200 requires external pull-up or pull-down resistors on certain pins. 5.3.1 Pull-down Resistor Requirements for TEST pins The MPC5200 requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1, TEST_SEL_1. Freescale Semiconductor < 1 Ω 10 µF 200-400 pF Figure 53. Power Supply Filtering MPC5200 Data Sheet, Rev. 4 ...

  • Page 74

    ... The JTAG interface can control the direction of the MPC5200 I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5200 comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released. For more details refer to the Reset and JTAG Timing Specification. 74 MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor ...

  • Page 75

    ... BDM MPC5200 Pin # I/O Pin 16 — 15 TEST_SEL_0 14 — 13 HRESET 12 — 11 SRESET 10 — 9 JTAG_TMS Freescale Semiconductor optional assertion of JTAG_TRST Figure 54. PORRESET vs. JTAG_TRST Table 53. COP/BDM Interface Signals BDM Internal Connector PullUp/Down GND — ckstp_out — KEY — hreset GND — sreset N/C — ...

  • Page 76

    ... Pull-Up tdi 100k Pull-Up 4 qack — tdo — Figure 55 allows the COP to assert HRESET or MPC5200 Data Sheet, Rev. 4 External 1 I/O PullUp/Down — — 10k Pull-Up O — — — I 10k Pull-Up O 10k Pull-Up O — O — I Freescale Semiconductor ...

  • Page 77

    ... Key Key Freescale Semiconductor 10Kohm HRESET SRESET 10Kohm 10Kohm TRST 10Kohm TMS 10Kohm TCK VDD 10Kohm TDI CKSTP_OUT TDO halted NC qack Figure 55. COP Connector Diagram MPC5200 Data Sheet, Rev. 4 System Design Information PORRESET MPC5200 HRESET VDD VDD SRESET VDD JTAG_TRST ...

  • Page 78

    ... JTAG interface without COP connector. PORRESET HRESET SRESET Figure 56. JTAG_TRST wiring for boards without COP connector 78 PORRESET MPC5200 HRESET 10Kohm VDD 10Kohm VDD SRESET JTAG_TRST 10Kohm VDD JTAG_TMS 10Kohm VDD JTAG_TCK 10Kohm VDD JTAG_TDI TEST_SEL_0 JTAG_TDO MPC5200 Data Sheet, Rev. 4 Freescale Semiconductor ...

  • Page 79

    ... PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors, Rev. 2: MPCFPE32B/AD [3] G2 Core Reference Manual, Rev. 0: G2CORERM/D [4] PCI Local Bus Specification, Revision 2.2, December 18, 1998 [5] ANSI ATA-4 Specification [6] IEEE 802.3 Specification (ETHERNET) Freescale Semiconductor Table 54. Ordering Information Speed Ambient Temp 400 0C to 70C 266 -40C to 85C 400 -40C to 85C ...

  • Page 80

    ... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...