MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 32

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NOTES:
1 t
2 All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender shall
32
the other agent to respond with a signal before proceeding.
stop generating STROBE edges t
the connector of the sender. Even though the sender stops generating STROBE edges, the receiver may receive additional
STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at
1.5 V.
UI
• t
• t
• t
, t
t
t
IORDYZ
ZIORDY
Sym
t
t
t
t
MLI
t
UI
MLI
LI
t
t
t
t
ZAH
RFS
ACK
ZAD
ENV
SS
AZ
SR
RP
is a limited time-out that has a defined maximum.
is an unlimited interlock that has no maximum time value.
, t
is a limited time-out that has a defined minimum.
LI
indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (sender or recipient) is waiting for
Min
160
20
20
20
50
—
—
—
—
MODE 0
0
0
(ns)
Max
10
70
50
75
20
—
—
—
—
—
—
Table 29. Ultra DMA Timing Specification (continued)
Min
125
—
20
20
—
—
—
20
50
MODE 1
0
0
(ns)
RFS
Max
10
70
30
60
20
after negation of DMARDY. STROBE and DMARDY timing measurements are taken at
—
—
—
—
—
—
Min
100
20
20
20
50
MPC5200B Data Sheet, Rev. 4
—
—
—
—
MODE 2
0
0
(ns)
Max
10
—
—
70
20
50
20
—
—
—
—
Setup and hold times for DMACK, before assertion or
Time from STROBE edge to negation of DMARQ or
assertion of STOP, when sender terminates a burst.
Ready-to-Final STROBE time—no STROBE edges
Maximum time allowed for output drivers to release
Pull-up time before allowing IORDY to be released.
STROBE to DMARDY time, if DMARDY is negated
before this long after STROBE edge, the recipient
Minimum delay time required for output drivers to
Ready-to-Pause time—the time recipient waits to
receives no more than one additional data word.
Minimum time drive waits before driving IORDY
are sent this long after negation of DMARDY.
Envelope time—from DMACK to STOP and
HDMARDY during data out burst initiation.
initiate pause after negating DMARDY.
assert or negate from released state
from being asserted or negated
Comment
negation.
Freescale Semiconductor
SpecID
A8.36
A8.37
A8.38
A8.39
A8.40
A8.41
A8.42
A8.43
A8.44
A8.45
A8.46