MPC8250AZUPIBC Freescale Semiconductor, MPC8250AZUPIBC Datasheet - Page 4

• Manufacturer Part Number: MPC8250AZUPIBC
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8250AZUPIBC

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Processor Series: MPC8xxx
• Core: 603e
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 300 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 300MHz
• Embedded Interface Type: I2C, JTAG, SPI, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 480
• Rohs Compliant: No
• Family Name: MPC82XX
• Device Core: PowerQUICC II
• Device Core Size: 32b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 2.2V
• Operating Supply Voltage (min): 1.9V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 480
• Package Type: TBGA
• For Use With: CWH-PPC-8248N-VE - KIT EVAL SYSTEM QUICCSTART 8248
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Features
4
•
•
— Dedicated interface logic for SDRAM
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
— One multichannel controller (MCC2)
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
— Two serial management controllers (SMCs), identical to those of the MPC860
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I
— Up to four TDM interfaces
for communications protocols
– 10/100-Mbit Ethernet/IEEE 802.3® CDMA/CS interface through media independent
– Transparent
– HDLC—Up to T3 rates (clear channel)
– Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
– Transparent
– UART (low-speed operation)
– Microwire compatible
– Multiple-master, single-master, and slave modes
– Supports one group of four TDM channels
interface (MII)
subgroups of 32 channels each.
interfaces up to four TDM interfaces per MCC
division-multiplexed (TDM) channels
MPC8250 Hardware Specifications, Rev. 2
2
C) controller (identical to the MPC860 I
2
C controller)
Freescale Semiconductor