MPC8349EVVALFB Freescale Semiconductor, MPC8349EVVALFB Datasheet - Page 86

• Manufacturer Part Number: MPC8349EVVALFB
• Description: IC MPU POWERQUICC II 672-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8349EVVALFB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 667MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 672-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8349E-MITXE
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: TBGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Family Name: MPC83xx
• Device Core: PowerQUICC II Pro
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.3V
• Operating Supply Voltage (max): 1.36V
• Operating Supply Voltage (min): 1.24V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: TBGA
• For Use With: MPC8349E-MITX-GP - KIT REFERENCE PLATFORM MPC8349EMPC8349E-MITXE - BOARD REFERENCE FOR MPC8349MPC8349EA-MDS-PB - KIT MODULAR DEV SYSTEM MPC8349E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document Revision History
86
Number
Rev.
3
2
1
0
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
11/2006
8/2006
4/2006
3/2006
Date
Initial public release.
• Updated note in introduction.
• In the features list in Section 1, “Overview,” updated DDR data rate to show 400 MHz for DDR2
•
• In Section 23, “Ordering Information,” replicated note from document introduction.
• Changed all references to revision 2.0 silicon to revision 3.0 silicon.
• Changed VIH minimum value in Table 40, “JTAG Interface DC Electrical Characteristics,” to
• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min
• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”
• In Table 66, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.
• Removed Table 20, “Timing Parameters for DDR2-400.”
• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC
• Changed Min and Max values for V
• In Table 55, “MPC8349EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout
• Table 55, “MPC8349EA (TBGA) Pinout Listing,” in row AVDD3 changed power supply from
for TBGA parts for silicon 3.x and 400 MHz for DDR2 for TBGA parts for silicon 3.x.
OV
= 2 and max = OV
Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.
Characteristics.”
Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that
MDICO be tied to GRD using an 18 Ω resistor and MCIC1 be tied to DDR power using an 18 Ω
resistor.’
“AVDD3” to ‘—.’
DD
Table 68. Document Revision History (continued)
– 0.3.
DD
+ 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.
Substantive Change(s)
IH
and VIL in Table 40Table 44,“PCI DC Electrical
Freescale Semiconductor