Z8018110FEG Zilog, Z8018110FEG Datasheet - Page 59

• Manufacturer Part Number: Z8018110FEG
• Description: IC 10MHZ ACCESS CTRL 100-QFP
• Manufacturer: Zilog

Specifications of Z8018110FEG

• Processor Type: Z180
• Features: Smart Access Controller SAC™
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Program Memory Size: 1 MB
• Interface Type: ASCI, UART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8018100ZCO
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4692; Z8018110FEG

Zilog
DS971800500
No
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
25a
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Symbol
tAH
tMED2
tRDD2
tM1D2
tDRS
tDRH
tSTD1
tSTD2
tWS
tWH
tWDZ
tWRD1
tWDO
tWRD2
tWRP
tWDH
tIOD1
tIOD2
tIOD3
tINTS
tINTH
tNMIW
tBRS
tBRH
tBAD1
tBAD2
tBZD
tMEWH
tMEWL
tRFD1
tRFD2
tHAD1
tHAD2
tDRQS
tDRQH
tTED1
Table A. Z180 CPU & 180 Peripherals Timing (Continued)
Parameter
Address Hold Time
(/MREQ, /IORQ, /RD, /WR)
Clock Fall to /MREQ Rise Delay
Clock Fall to /RD Rise Delay
Clock Rise to /M1 Rise Delay
Data Read Setup Time
Data Read Hold Time
Clock Fall to ST Fall
Clock Fall to ST Rise
/WAIT Setup Time to Clock Fall
/WAIT Hold time from Clock Fall
Clock Rise to Data Float Delay
Clock Rise to /WR Fall Delay
/WR fall to Data Out Delay
Clock Fall to /WR Rise
/WR Pulse Width
(Memory Write Cycles)
/WR Pulse Width (I/O Write Cycles)
Write Data Hold Time from /WR Rise
Clock Fall to /IORQ Fall Delay
(/IOC=1)
Clock Rise to /IORQ Fall Delay
(/IOC=0)
Clock Fall /IOQR Rise Delay
/M1 Fall to /IORQ Fall Delay
/INT Setup Time to Clock Fall
/INT Hold Time from Clock Fall
/NMI Pulse Width
/BUSREQ Setup Time to Clock Fall
/BUSREQ Hold Time from Clock Fall
Clock Rise to /BUSACK Fall Delay
Clock Fall to /BUSACK Rise Delay
Clock Rise to Bus Floating Delay Time
/MREQ Pulse Width (High)
/MREQ Pulse Width (Low)
Clock Rise to /RFSH Fall Delay
Clock Rise to /RFSH Rise Delay
Clock Rise to /HALT Fall Delay
Clock Rise to /HALT Rise Delay
/DREQi Setup Time to Clock Rise
/DREQi Hold Time from Clock Rise
Clock Fall to /TENDi Fall Delay
PS009701-0301
Min
110
210
200
10
25
30
30
10
30
30
80
30
30
70
80
30
30
0
Z8018110
Max
50
50
60
60
60
60
50
10
50
50
55
50
60
60
80
60
60
50
50
50
S
MART
A
CCESS
Unit
C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ONTROLLER
Z80181
2-59
SAC
™