Z8018110FEG Zilog, Z8018110FEG Datasheet - Page 68

• Manufacturer Part Number: Z8018110FEG
• Description: IC 10MHZ ACCESS CTRL 100-QFP
• Manufacturer: Zilog

Specifications of Z8018110FEG

• Processor Type: Z180
• Features: Smart Access Controller SAC™
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Program Memory Size: 1 MB
• Interface Type: ASCI, UART
• Maximum Clock Frequency: 10 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8018100ZCO
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4692; Z8018110FEG

Zilog
AC CHARACTERISTICS (Continued)
Interrupt Daisy-Chain Timing
Figure 74 shows the interrupt daisy-chain timing. Parame-
ters referenced in this figure appear in Table G.
2-68
/IORQ
(SCC)
/WAIT
Data
CLK
/INT
/M1
IEO
No
1
2
3
4
5
6
7
8
9
10
11
IEI
Symbol
TsM1(Cr)
TsM1(IO)INTA
Th
TdM1r(DOz)
TdCr(DO)
TsIEI(TW4)
TdIEIf(IEOf)
TdIEIr(IEOr)
TdM1f(IEOf)
TdCWA(f)INTA
TdCWA(r)INTA
1
9
Table G. Interrupt Daisy-Chain Timing Parameters
10
Figure 74. Interrupt Daisy-Chain Timing
2
Parameter
/M1 Fall to Clock Rise Setup Time
/M1 Fall to /IORQ Fall Setup Time
(During INTACK Cycle)
Hold Time
/M1 Rise to Data Out Float Delay
Clock Rise to Data Out Delay
IEI to T
IEI Fall to IEO Fall Delay
IEO Rise to IEO Rise Delay
/M1 Fall to IEO Fall Delay
Clock Rise to /WAIT Fall Delay
Clock Rise to /WAIT Rise Delay
PS009701-0301
W4
Rise Setup Time
6
7, 8
5
11
2TcC
Min
20
95
0
0
Z8018110
S
MART
Max
A
3
4
CCESS
C
DS971800500
ONTROLLER
Unit
ns
ns
ns
ns
Z80181
SAC
™