MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet

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... The MPC862P, which contains a PowerPC™ core processor, is the superset device of the MPC862/857T/857DSL family. For functional characteristics of the processor, refer to the MPC862 PowerQUICC™ Family Users Manual (MPC862UM/D). © Freescale Semiconductor, Inc., 2006. All rights reserved. Document Number: MPC862EC Rev. 3, 2/2006 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 ...

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... MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces and 16 protection groups — Advanced on-chip-emulation debug mode MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 1. MPC862 Family Functionality Cache Data Cache Cache 16 Kbyte 8 Kbyte Kbyte 4 Kbyte Kbyte 4 Kbyte 4 Kbyte 4 Kbyte Ethernet SCC SMC 10T 10/100 Table 1). Freescale Semiconductor ...

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... Interrupt can be masked on reference match and event capture • Fast Ethernet controller (FEC) — Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA multiplexed bus. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 2 C can be relocated without RAM-based microcode Features 3 ...

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... Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation — HDLC/SDLC — HDLC bus (implements an HDLC-based local area network (LAN)) — Asynchronous HDLC to support PPP (point-to-point protocol) — AppleTalk MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev GRACEFUL STOP TRANSMIT ) , ENTER HUNT Freescale Semiconductor ...

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... I/O windows supported • Low power support — Full on—All units fully powered — Doze—Core functional units disabled except time base decrementer, PLL, memory controller, RTC, and CPM in low-power standby MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 2 C) port Features 5 ...

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... The MPC862/857T/857DSL is comprised of three modules that each use the 32-bit internal bus: the MPC8xx core, the system integration unit (SIU), and the communication processor module (CPM). The MPC862P/862T block diagram is shown in Figure 2. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Figure 1. The MPC857T/857DSL block diagram is shown in Freescale Semiconductor ...

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... FIFOs 10/100 Base-T Media Access Control Parallel Interface Port MII *The MPC862T contains 4-Kbyte instruction cache and 4-Kbyte data cache. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 16-Kbyte* Instruction Cache Unified Instruction MMU Bus 32-Entry ITLB 8-Kbyte* Data Cache ...

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... VDDSYN -0.3 to 4.0 System Interface Unit (SIU) Memory Controller Internal External Bus Interface Bus Interface Unit Unit System Functions Real-Time Clock PCMCIA/ATA Interface 8-Kbyte 10 Serial and 2 Independent DMA Channels 2 SMC1 SMC2* SPI I C Max Freq Unit (MHz Freescale Semiconductor ...

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... Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or V MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor (GND = 0 V) Symbol Value V GND-0 ...

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... Single layer board (1s) Four layer board (2s2p) Table 4. Power Dissipation ( Frequency Typical Maximum 50 MHz 656 66 MHz TBD 50 MHz 630 66 MHz 890 Symbol Value Unit °C/W θ θJMA θJMA θJMA R 13 θ θJC Ψ Ψ Unit 735 mW TBD mW 760 mW 1000 mW Freescale Semiconductor ...

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... Input Leakage Current, Vin = 0 V (Except TMS, TRST, DSCK, and DSDI pins) 2 Input Capacitance Output High Voltage, IOH = -2.0 mA, VDDH = 3.0 V (Except XTAL, XFC, and Open drain pins) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 4. Power Dissipation (P ) (continued Frequency Typical ...

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... However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity T MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Symbol VOL = (VDD x IDD) + PI/O, where PI/O is the power dissipation of the I °C can be obtained from the equation are possible Min Max Unit — 0 standard. Freescale Semiconductor ...

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... Board Temperture Rise Above Ambient Divided by Package Figure 3. Effect of Board Temperature Rise on Thermal Behavior MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor . For instance, the user can change the air flow around θ Power Thermal Calculation and Measurement 80 13 ...

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... The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev can be used to determine the junction temperature with a JT Freescale Semiconductor ...

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... Freq Min Max Period 20.00 30.30 MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor power supply should be bypassed to ground CC and GND circuits. Pull up all unused inputs or signals that will be CC Table 6 shows the period ranges for standard part frequencies. 66 MHz ...

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... Freescale Semiconductor ...

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... B16b BB, BG, BR, valid to CLKOUT (setup 6 time) (4MIN = 0. 0.00) B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (hold time) (MIN = 0. 1.00 ) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 7. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 7.60 13.80 6.30 7 ...

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... Freescale Semiconductor Unit ...

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... TRLX = 0,1 & CSNT = 0 (MIN = 0. 2.00) B29c CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 0. 2.00) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 7. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 35.90 — ...

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... Freescale Semiconductor Unit ...

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... UPM, EBDF = 0 (MAX = 0. 6.80) B32b CLKOUT rising edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM (MAX = 0. 8.00) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 7. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 8.40 — ...

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... Freescale Semiconductor Unit ...

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... B37 and B38 are specified to enable the freeze of the UPM output signals as described in 13 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 22. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 7. Bus Operation Timings (continued) 33 MHz 40 MHz Min Max Min 6.00 — ...

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... CLKOUT MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev 0 2.0 V 2.0 V 0 2.0 V 2.0 V 0 2.0 V 2.0 V 0 2.0 V 0.8 V Figure 4. Control Timing Figure 5. External Clock Timing 2 2 Freescale Semiconductor ...

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... Figure 6. Synchronous Output Signals Timing Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B8 B9 B8a B9 B8b B11 B12 B11a ...

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... It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT TA D[0:31], DP[0:3] MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev B16 B16a B17a B16b B16 B17 B18 B19 Figure 9. Input Data Timing in Normal Case B17 B17 Freescale Semiconductor ...

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... GPCM factors. CLKOUT TS A[0:31] CSx OE WE[0:3] D[0:31], DP[0:3] Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B20 B21 Memory Controller and DLT3 = 1 B11 B12 B8 B22 B25 B28 B18 Bus Signal Timing ...

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... A[0:31] CSx OE D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev B11 B12 B8 B22a B24 B25 B18 B11 B12 B8 B22b B22c B24a B25 B18 B23 B26 B19 B23 B26 B19 Freescale Semiconductor ...

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... CLKOUT B11 TS A[0:31] CSx OE D[0:31], DP[0:3] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 1, MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B12 B8 B22a B27 B27a B22b B22c B18 ACS = 10, ACS = 11) Bus Signal Timing B23 B26 B19 29 ...

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... GPCM factors. CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0,1 CSNT = 0) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev B11 B12 B8 B22 B25 B26 B8 B30 B23 B28 B29b B29 B9 Freescale Semiconductor ...

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... CLKOUT TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0,1 CSNT = 1) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B11 B12 B8 B22 B28b B28d B25 B26 B28a B28c B8 Bus Signal Timing B30a B30c B23 B29c B29g ...

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... B11 TS A[0:31] CSx WE[0:3] OE D[0:31], DP[0:3] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0,1, CSNT = 1) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev B12 B8 B22 B28b B28d B25 B26 B8 B28a B28c B30b B30d B23 B29e B29i B29d B29h B29b B9 Freescale Semiconductor ...

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... UPM. CLKOUT A[0:31] CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 18. External Bus Timing (UPM Controlled Signals) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B8 B31a B31d B31 B34 B34a B34b B32a B32d B32 ...

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... UPWAIT signal controlled by the UPM. CLKOUT B37 UPWAIT CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev B38 Cycles Timing B38 Cycles Timing Freescale Semiconductor ...

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... AS CSx, WE[0:3], OE, GPLx, BS[0:3] Figure 23. Asynchronous External Master—Control Signals Negation Timing MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor B41 B42 B40 (GPCM Handled ACS = 00) B39 B40 (GPCM Controlled—ACS = 00) ...

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... IRQx Figure 25. Interrupt Detection Timing for External Edge Sensitive Lines MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 8. Interrupt Timing 1 Characteristic 4xT I39 I40 I41 I43 All Frequencies Unit Min Max 6.00 ns 2.00 ns 3.00 ns 3.00 ns — CLOCKOUT I42 I43 Freescale Semiconductor ...

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... These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only detected 2 cycles before the PSL timer expiration. See PCMCIA Interface in the MPC862 PowerQUICC User s Manual . MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 9. PCMCIA Timing 33 MHz 40 MHz ...

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... PCMCIA access cycle timing for the external bus read. CLKOUT TS A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 26. PCMCIA Access Cycles Timing External Bus Read MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev P44 P46 P45 P48 P50 P52 P53 B18 P47 P49 P51 P52 B19 Freescale Semiconductor ...

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... D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITx Figure 28. PCMCIA WAIT Signals Detection Timing MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor P44 P46 P45 P48 P50 P52 P53 ...

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... Figure 29. PCMCIA Output Port Timing P59 P60 Figure 30. PCMCIA Input Port Timing 50 MHz 66 MHz Max Min Max Min Max — 19.00 — 19.00 — 18.00 — 14.40 — — 5.00 — 5.00 — — 1.00 — 1.00 — Freescale Semiconductor Unit ...

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... Figure 31 provides the input timing for the debug port clock. DSCK Figure 32 provides the timing for the debug port. DSCK DSDI DSDO MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 11. Debug Port Timing All Frequencies Min CLOCKOUT 1. CLOCKOUT 0.00 8 ...

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... Freescale Semiconductor ...

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... CLKOUT HRESET RSTCONF D[0:31] (OUT) (Weak) Figure 34. Reset Timing—Data Bus Weak Drive during Configuration MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor R71 R76 R73 R74 R75 R69 R79 ...

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... R81 Figure 36 though Figure All Frequencies Min Max 100.00 — 40.00 — 0.00 10.00 5.00 — 25.00 — — 27.00 0.00 — — 20.00 100.00 — 40.00 — — 50.00 — 50.00 — 50.00 50.00 — 50.00 — Freescale Semiconductor 39. Unit ...

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... Figure 37. JTAG Test Access Port Timing Diagram TCK TRST TCK Output Signals Output Signals Output Signals Figure 39. Boundary Scan (JTAG) Timing Diagram MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor J82 J83 J82 J84 Figure 36. JTAG Test Clock Input Timing J85 J86 J87 J88 J91 J90 Figure 38 ...

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... MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Figure 40 Table 14. PIP/PIO Timing Characteristic though Figure 44. All Frequencies Unit Min Max 0 — 2.5 – t3 — clk 1.5 — clk 1 clk – — — clk 5 — clk — 2 clk 2 — clk 15 — ns 7.5 — ns — Freescale Semiconductor ...

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... Figure 41. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 42. PIP Rx (Pulse Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 43. PIP TX (Pulse Mode) Timing Diagram MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor CPM Electrical Characteristics 26 22 ...

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... MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 15. Port C Interrupt Timing Characteristic 35 Figure 45. Port C Interrupt Detection Timing Figure 46 Table 16. IDMA Controller Timing Characteristic 30 33.34 MHz Unit Min Max 55 — — though Figure 49. All Frequencies Unit Min Max 7 — — ns — Freescale Semiconductor ...

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... Figure 46. IDMA External Requests Timing Diagram CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 47. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Characteristic CPM Electrical Characteristics All Frequencies Unit Min Max — — ...

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... CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 48. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 49. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Freescale Semiconductor ...

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... TIN/TGATE rise and fall time 62 TIN/TGATE low time 63 TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO low to TOUT valid MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 17. Baud Rate Generator Timing Characteristic Table 18. Timer Timing Characteristic CPM Electrical Characteristics Figure 50 ...

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... All Frequencies Min Max — SYNCCLK/2.5 MHz — — — 15.00 20.00 — 35.00 — — 15.00 17.00 — 13.00 — 10.00 45.00 10.00 45.00 10.00 45.00 10.00 55.00 10.00 55.00 0.00 42.00 — 16.00 or MHz SYNCCLK — Freescale Semiconductor Unit ...

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... CE=0) (Input) 71 L1RCLK (FE=1, CE=1) (Input) L1RSYNC (Input) 73 L1RXD (Input) L1ST(4-1) (Output) Figure 52. SI Receive Timing Diagram with Normal Clocking (DSC = 0) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 19. SI Timing (continued) Characteristic 71a 72 RFSD BIT0 76 78 CPM Electrical Characteristics ...

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... CPM Electrical Characteristics L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 53. SI Receive Timing with Double-Speed Clocking (DSC = 1) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev 83a RFSD=1 77 BIT0 Freescale Semiconductor ...

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... L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) L1TXD (Output) L1ST(4-1) (Output) Figure 54. SI Transmit Timing Diagram (DSC = 0) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 70 72 TFSD 80a BIT0 80 78 CPM Electrical Characteristics ...

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... CPM Electrical Characteristics L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) 75 L1RSYNC (Input) 73 L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 55. SI Transmit Timing with Double Speed Clocking (DSC = 1) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev 83a 82 TFSD Freescale Semiconductor ...

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... MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Figure 56. IDL Timing CPM Electrical Characteristics 57 ...

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... All Frequencies Min Max 0.00 SYNCCLK/3 — — 0.00 30.00 0.00 30.00 40.00 — 40.00 — 0.00 — 40.00 — Freescale Semiconductor Unit Unit MHz ...

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... Figure 57. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 58. SCC NMSI Transmit Timing Diagram MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 102 101 100 107 102 101 100 103 105 104 CPM Electrical Characteristics 108 ...

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... MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev 102 101 100 103 104 107 105 Figure 59. HDLC Bus Timing Diagram Figure 60 though Table 22. Ethernet Timing Characteristic 104 Figure 64. All Frequencies Unit Min Max 40 — ns — — 120 ns 20 — — — ns 100 — ns — — 101 Freescale Semiconductor ...

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... CLSN(CTS1) (Input) Figure 60. Ethernet Collision Timing Diagram RCLK1 RxD1 (Input) RENA(CD1) (Input) Figure 61. Ethernet Receive Timing Diagram MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 22. Ethernet Timing (continued) Characteristic 2 2 120 121 124 125 CPM Electrical Characteristics All Frequencies ...

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... RxD1 0 (Input) Start Frame Delimiter RSTRT (Output) Figure 63. CAM Interface Receive Start Timing Diagram REJECT Figure 64. CAM Interface REJECT Timing Diagram MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev 128 121 132 1 1 BIT1 125 137 129 134 BIT2 136 Freescale Semiconductor ...

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... SMTXD (Output) SMSYNC SMRXD (Input) NOTE: 1. This delay is equal to an integer number of character-length clocks. Figure 65. SMC Transparent Timing Diagram MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Figure Table 23. SMC Transparent Timing Characteristic 152 151 151A 150 NOTE 1 154 155 ...

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... MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Figure 66 Table 24. SPI Master Timing Characteristic 167 166 160 167 162 166 Data lsb 165 164 166 Data lsb though Figure 67. All Frequencies Min Max 4 1024 2 512 15 — 0 — — — — 15 — 15 msb msb Freescale Semiconductor Unit t cyc t cyc ...

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... Slave sequential transfer delay (does not require deselect) 175 Slave data setup time (inputs) 176 Slave data hold time (inputs) 177 Slave access time MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 167 166 160 167 166 Data 165 msb ...

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... Data lsb 179 181 182 Data lsb 172 170 182 181 181 182 180 msb Data 179 176 181 182 msb Data 171 174 178 Undef msb msb 174 178 msb lsb msb lsb Freescale Semiconductor ...

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... SDL/SCL fall time 211 Stop condition setup time 1 SCL frequency is given by SCL = BrgClk_frequency / ((BRG register + 3) * pre_scaler * 2). The ratio SyncClk/(Brg_Clk/pre_scaler) must be greater or equal to 4/1. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 2 Table 26 Timing (SCL < 100 KH Characteristic 1 2 Table 27 Timing (SCL > ...

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... UTPB, SOC active delay (and PHREQ and PHSEL active delay in MPHY mode) MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev 204 207 209 210 2 Figure 70 Bus Timing Diagram Direction 208 211 Min Max Unit Output MHz Input 4ns MHz Output Input Input Output Freescale Semiconductor ...

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... This section provides the AC electrical specifications for the Fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Furthermore, MII signals use TTL signal levels compatible with devices operating at either 5.0 or 3.3 V. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Figure 71 ...

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... MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 29. MII Receive Signal Timing Characteristic Table 30. MII Transmit Signal Timing Characteristic Min Max Unit 5 — — ns 35% 65% MII_RX_CLK period 35% 65% MII_RX_CLK period M4 Min Max Unit 5 — ns — 25 Freescale Semiconductor ...

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... Table 32 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Characteristic Table 31. MII Async Inputs Signal Timing ...

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... M13 Table 33. MPC862/857T/857DSL Derivatives Ethernet Multi-Channel ATM Support Support HDLC Support Yes Yes Min Max Unit 0 — ns — — — ns 40% 60% MII_MDC period 40% 60% MII_MDC period MM15 M10 M11 Cache Size Instruction Data Yes 4 Kbytes 4 Kbytes Yes 16 Kbytes 8 Kbytes Freescale Semiconductor ...

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... Pin Assignments . Figure 77 shows the top view pinout of the PBGA package. For additional information, see the MPC862 PowerQUICC Family User s Manual. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet Multi-Channel ATM Support Support HDLC Support Yes addresses ...

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... IPB6 ALEA IRQ4 IPB5 IPB1 IPB2 ALEB M_COL IRQ2 IPB0 IPB7 BR IRQ6 IPB4 IPB3 GND VDDL TS IRQ3 BURST VDDH CS3 CS6 CS2 GPLA5 BDIP TEA WE0 GPLA1 GPLA3 CS7 CS0 TA GPLA4 CS5 CE1A WR GPLB4 WE1 WE3 CS4 CE2A CS1 Freescale Semiconductor ...

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... V12, V6, W5, U6, T7 DP0 V3 IRQ3 DP1 V5 IRQ4 DP2 W4 IRQ5 DP3 V4 IRQ6 MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 35. Pin Assignments Pin Number Mechanical Data and Ordering Information Type Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state Bidirectional Three-state ...

Page 76

... GPL_A4 UPWAITB B1 GPL_B4 MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 35. Pin Assignments (continued) Pin Number Type Bidirectional Bidirectional Bidirectional Active Pull-up Bidirectional Input Input Input Output Output Output Output Output Output Output Output Output Output Output Bidirectional Bidirectional Freescale Semiconductor ...

Page 77

... MII-RXD0 IP_A4 U4 2 UTPB_Split4 MII-RXCLK IP_A5 U5 2 UTPB_Split5 MII-RXERR MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 35. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Output Input Input Open-drain Open-drain Analog Output Analog Input (3.3 V only) ...

Page 78

... DSDO BADDR30 K4 REG BADDR[28:29] M3 MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 35. Pin Assignments (continued) Pin Number Type Input Input Bidirectional Three-state Bidirectional Bidirectional Three-state Bidirectional Bidirectional Bidirectional Bidirectional Three-state Bidirectional Three-state Bidirectional Output Bidirectional Bidirectional Output Output Input Freescale Semiconductor ...

Page 79

... BRGO2 TIN2 PA4 P19 CLK4 TOUT2 PA3 P17 CLK5 BRGO3 TIN3 MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 35. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional Bidirectional (Optional: Open-drain) Bidirectional Bidirectional (Optional: Open-drain) Bidirectional ...

Page 80

... Table 35. Pin Assignments (continued) Pin Number Type Bidirectional Bidirectional Bidirectional Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Freescale Semiconductor ...

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... D16 DREQ0 RTS1 L1ST1 RxClav PC14 D18 DREQ1 RTS2 L1ST2 MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 35. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional (Optional: Open-drain) Bidirectional ...

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... MII-RXD3 UTPB0 PD14 V19 L1RSYNCA MII-RXD2 UTPB1 PD13 V18 L1TSYNCB MII-RXD1 UTPB2 MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 35. Pin Assignments (continued) Pin Number Type Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Freescale Semiconductor ...

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... W16 REJECT4 MII-TXD1 SOC TMS G18 TDI H17 DSDI TCK H16 DSCK MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Table 35. Pin Assignments (continued) Pin Number Mechanical Data and Ordering Information Type Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional ...

Page 84

... AN1231/D) available from your local Freescale sales office. of the PBGA package. MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 35. Pin Assignments (continued) Pin Number Figure 78 Type Input Output Input Bidirectional Output Input Power Power Power Power No-connect shows the mechanical dimensions Freescale Semiconductor ...

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... BOTTOM VIEW Figure 78. Mechanical Dimensions and Bottom Surface Nomenclature MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor 4X 0 18X e NOTES: 1. Dimensions and tolerancing per ASME Y14.5M, 1994. 2. Dimensions in millimeters. 3. Dimension b is the maximum solder bal measured parallel to datum 357X ...

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... Updated document template. 3.0 2/2006 • Changed Tj from 95C to 105C in table 34 MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev Table 36. Document Revision History Substantive Changes Table 7 B23 max value @ 66 MHz from ns. Table 5 DC Electrical Specifications about meeting the VIL Max Freescale Semiconductor ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3 Freescale Semiconductor Document Revision History 87 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...