MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet - Page 35

IC MPU POWERQUICC 50MHZ 357-PBGA

MPC857DSLVR50B

Manufacturer Part Number
MPC857DSLVR50B
Description
IC MPU POWERQUICC 50MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC857DSLVR50B

Processor Type
MPC8xx PowerQUICC 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Processor Series
MPC85xx
Core
MPC8xx
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Operating Supply Voltage
2.5 V, 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Family Name
MPC8xx
Device Core
PowerQUICC
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.465/3.6V
Operating Supply Voltage (min)
2/3.135V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
357
Package Type
BGA
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC857DSLVR50B
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC857DSLVR50B
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure 21
Figure 22
GPCM.
Figure 23
Freescale Semiconductor
CSx, WE[0:3],
R/W, BURST
provides the timing for the synchronous external master access controlled by the GPCM.
provides the timing for the asynchronous external master memory access controlled by the
provides the timing for the asynchronous external master control signals negation.
TSIZ[0:1],
CLKOUT
OE, GPLx,
TSIZ[0:1],
A[0:31],
CLKOUT
A[0:31],
BS[0:3]
R/W
CSx
Figure 23. Asynchronous External Master—Control Signals Negation Timing
AS
CSx
TS
AS
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Figure 22. Asynchronous External Master Memory Access Timing
Figure 21. Synchronous External Master Access Timing
(GPCM Controlled—ACS = 00)
(GPCM Handled ACS = 00)
B40
B39
B41
B40
B42
B43
B22
B22
Bus Signal Timing
35

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