MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet - Page 71

• Manufacturer Part Number: MPC857DSLVR50B
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC857DSLVR50B

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC85xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 74
13.3
Table 31
Figure 75
13.4
Table 32
correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under
investigation.
Freescale Semiconductor
Num
Num
M7
M8
M9
provides information on the MII async inputs signal timing.
provides information on the MII serial management channel signal timing. The FEC functions
MII Async Inputs Signal Timing (MII_CRS, MII_COL)
MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
shows the MII transmit signal timing diagram.
shows the MII asynchronous inputs signal timing diagram.
MII_TXD[3:0] (outputs)
MII_TX_EN
MII_TX_ER
MII_TX_CLK (input)
MII_TX_CLK pulse width high
MII_TX_CLK pulse width low
MII_CRS, MII_COL minimum pulse width
MII_CRS, MII_COL
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Table 30. MII Transmit Signal Timing (continued)
Figure 74. MII Transmit Signal Timing Diagram
Figure 75. MII Async Inputs Timing Diagram
Characteristic
Characteristic
Table 31. MII Async Inputs Signal Timing
M5
M6
M7
M9
M8
35%
35%
Min
Min
1.5
65%
65%
Max
Max
—
FEC Electrical Characteristics
MII_TX_CLK period
MII_TX_CLK period
MII_TX_CLK period
Unit
Unit
71