MPC8347VVAGDB Freescale Semiconductor, MPC8347VVAGDB Datasheet - Page 48

IC MPU POWERQUICC II 672-PBGA

MPC8347VVAGDB

Manufacturer Part Number
MPC8347VVAGDB
Description
IC MPU POWERQUICC II 672-PBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC II PROr
Datasheets

Specifications of MPC8347VVAGDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8349E-MITXE
Maximum Clock Frequency
400 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
Family Name
MPC83xx
Device Core
PowerQUICC II Pro
Device Core Size
32b
Frequency (max)
400MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2V
Operating Supply Voltage (max)
1.26V
Operating Supply Voltage (min)
1.14V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
TBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
400MHz
Embedded Interface Type
I2C, SPI, USB, UART
Digital Ic Case Style
TBGA
No. Of Pins
672
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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PCI
Table 42
Figure 33
48
Input hold from clock
Notes:
1. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a
2. The symbols for timing specifications follow the pattern of t
3. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
4. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
5. Input timings are measured at the pin.
Clock to output valid
Output hold from clock
Clock to output high impedance
Input setup to clock
Input hold from clock
Notes:
1. The symbols for timing specifications follow the pattern of t
2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications .
3. For active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered through the
4. Input timings are measured at the pin.
description of M66EN.
and t
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t
to the high (H) state or setup time. Also, t
high (H) relative to the frame signal (F) going to the valid (V) state.
component pin is less than or equal to the leakage current specification.
and t
respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, t
to the high (H) state or setup time. Also, t
high (H) relative to the frame signal (F) going to the valid (V) state.
component pin is less than or equal to the leakage current specification.
(first two letters of functional block)(reference)(state)(signal)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
provides the PCI AC timing specifications at 33 MHz.
provides the AC test load for PCI.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Parameter
Parameter
Table 41. PCI AC Timing Specifications at 66 MHz
Output
Table 42. PCI AC Timing Specifications at 33 MHz
PCRHFV
PCRHFV
Figure 33. PCI AC Test Load
Z
0
symbolizes PCI timing (PC) with respect to the time hard reset (R) went
symbolizes PCI timing (PC) with respect to the time hard reset (R) went
= 50 Ω
Symbol
Symbol
t
t
t
PCKHOV
PCKHOX
t
t
t
for outputs. For example, t
PCKHOZ
for outputs. For example, t
PCIXKH
PCIVKH
PCIXKH
(first two letters of functional block)(signal)(state)(reference)(state)
(first two letters of functional block)(signal)(state)(reference)(state)
2
1
R
L
Min
Min
3.0
= 50 Ω
0
2
0
1
PCIVKH
PCIVKH
(continued)
OV
DD
symbolizes PCI timing (PC) with
symbolizes PCI timing (PC) with
Max
Max
11
14
/2
Freescale Semiconductor
SYS
SYS
, reference (K) going
, reference (K) going
Unit
Unit
ns
ns
ns
ns
ns
ns
for inputs
for inputs
Notes
Notes
3, 5
2, 3
2, 4
2, 4
2
2

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