MC68EC000EI20 Freescale Semiconductor, MC68EC000EI20 Datasheet - Page 486

• Manufacturer Part Number: MC68EC000EI20
• Description: IC MPU 32BIT 20MHZ 68-PLCC
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC000EI20

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Supervisor (Privileged) Instructions
PFLUSH
Operation:
Assembler
Syntax:
Attributes:
Description: PFLUSH invalidates address translation cache entries. The instruction has
Condition Codes:
MMU Status Register:
6-32
Not affected.
Not affected.
three forms. The PFLUSHA instruction invalidates all entries. When the instruction
specifies a function code and mask, the instruction invalidates all entries for a selected
function code(s). When the instruction also specifies an < ea > , the instruction
invalidates the page descriptor for that effective address entry in each selected function
code.
The mask operand contains three bits that correspond to the three function code bits.
Each bit in the mask that is set to one indicates that the corresponding bit of the FC
operand applies to the operation. Each bit in the mask that is zero indicates a bit of FC
and of the ignored function code. For example, a mask operand of 100 causes the
instruction to consider only the most significant bit of the FC operand. If the FC operand
is 001, function codes 000, 001, 010, and 011 are selected.
The FC operand is specified in one of the following ways:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
the instruction.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL
If Supervisor State
Else TRAP
PFLUSHA
PFLUSH FC,MASK
PFLUSH FC,MASK, < ea >
Unsized
Then Invalidate ATC Entries for Destination Addresses
Flush Entry in the ATC
(MC68030 only)
PFLUSH
MOTOROLA