YW80C188EC20 Intel, YW80C188EC20 Datasheet - Page 12

• Manufacturer Part Number: YW80C188EC20
• Description: IC MPU 16-BIT 5V 20MHZ 100-SQFP
• Manufacturer: Intel

Specifications of YW80C188EC20

• Processor Type: 80C188
• Features: EC suffix, 16-Bit, Extended Temp
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Family Name: Intel186
• Device Core: 8088
• Device Core Size: 16b
• Frequency (max): 20MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: SQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 864139

80C186EC 188EC 80L186EC 188EC
NOTE
Pin names in parentheses apply to the 80C188EC 80L188EC
12
Pin Name
RD
WR
READY
DEN
DT R
LOCK
HOLD
HLDA
NCS
ERROR
Type
I O
Pin
O
O
O
O
O
O
I
I
I
(Note 1)
Input
Type
A(L)
S(L)
A(L)
A(L)
A(L)
Table 2 Pin Descriptions (Continued)
Output
States
H(Z)
R(Z)
H(Z)
R(Z)
H(Z)
R(Z)
H(Z)
R(Z)
P(X)
H(Z)
R(Z)
P(X)
H(1)
R(0)
H(1)
R(1)
P(1)
P(1)
P(1)
P(0)
P(1)
I(X)
I(X)
I(1)
I(1)
I(1)
I(0)
I(1)
ReaD output signals that the accessed memory or I O
device should drive data information onto the data bus
WRite output signals that data available on the data bus are
to be written into the accessed memory or I O device
READY input to signal the completion of a bus cycle READY
must be active to terminate any 80C186EC bus cycle unless
it is ignored by correctly programming the Chip-Select unit
Data ENable output to control the enable of bi-directional
transceivers in a buffered system DEN is active only when
data is to be transferred on the bus
Data Transmit Receive output controls the direction of a bi-
directional buffer in a buffered system
LOCK output indicates that the bus cycle in progress is not
interruptable The processor will not service other bus
requests (such as HOLD) while LOCK is active This pin is
configured as a weakly held high input while RESIN is active
and must not be driven low
HOLD request input to signal that an external bus master
wishes to gain control of the local bus The processor will
relinquish control of the local bus between instruction
boundaries that are not LOCKed
HoLD Acknowledge output to indicate that the processor
has relinquished control of the local bus When HLDA is
asserted the processor will (or has) floated its data bus and
control signals allowing another bus master to drive the
signals directly
Numerics Coprocessor Select output is generated when
acessing a numerics coprocessor This signal does not exist
on the 80C188EC 80L188EC
ERROR input that indicates the last numerics processor
extension operation resulted in an exception condition An
interrupt TYPE 16 is generated if ERROR is sampled active
at the beginning of a numerics operation Systems not using
an 80C187 must tie ERROR to V
exist on the 80C188EC 80L188EC
Pin Description
CC
This signal does not