YW80C188EC20 Intel, YW80C188EC20 Datasheet - Page 8

• Manufacturer Part Number: YW80C188EC20
• Description: IC MPU 16-BIT 5V 20MHZ 100-SQFP
• Manufacturer: Intel

Specifications of YW80C188EC20

• Processor Type: 80C188
• Features: EC suffix, 16-Bit, Extended Temp
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-SQFP
• Family Name: Intel186
• Device Core: 8088
• Device Core Size: 16b
• Frequency (max): 20MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: SQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 864139

80C186EC/188EC, 80L186EC/188EC
pulled low for four clock cycles. Logically ANDing
the WDTOUT pin with the power-on reset signal al-
lows the WDT to reset the device in the event of a
WDT timeout. If a less drastic method of recovery is
desired. WDTOUT can be connected directly to NMI
or one of the INT input pins. The WDT may also be
used as a general purpose timer.
Power Management Unit
The 80C186EC Power Management Unit (PMU) is
provided to control the power consumption of the
device. The PMU provides four power management
modes: Active, Powersave, Idle and Powerdown.
Active Mode indicates that all units on the
80C186EC are operating at ½ the CLKIN frequency.
Idle Mode freezes the clocks of the Execution and
Bus units at a logic zero state (all peripherals contin-
ue to operate normally).
The Powerdown Mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator.
In Powersave Mode, all internal clock signals are di-
vided by a programmable prescalar (up to
normal frequency). Powersave Mode can be used
with Idle Mode as well as during normal (Active
Mode) operation.
80C187 Interface (80C186EC only)
The 80C186EC supports the direct connection of
the 80C187 Numerics Processor Extension. The
80C187 can dramatically improve the performance
of calculation intensive applications.
ONCE Test Mode
To facilitate testing and inspection of devices when
fixed into a target system, the 80C186EC has a test
mode available which forces all output and input/
output pins to be placed in the high-impedance
state. ONCE stands for ‘‘ON Circuit Emulation’’,
The ONCE mode is selected by forcing the
A19/S6/ONCE pin low during a processor reset
(this pin is weakly held high during reset to prevent
inadvertant entrance into ONCE Mode).
PACKAGE INFORMATION
This section describes the pin functions, pinout and
thermal characteristics for the 80C186EC in the
Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ
Quad Flat Pack (QFP) and the Shrink Quad Flat
Pack (SQFP). For complete package specifications
8
1/64
the
1. To address the fact that many of the package prefix variables
and information, see the Intel Packaging Outlines
and Dimensions Guide (Order Number: 231369).
Prefix Identification
Table 1 lists the prefix identifications.
NOTE:
1. The 5V 25 MHz version is only available in commercial
Pin Descriptions
Each pin or logical set of pins is described in Table
2, There are four columns for each entry in the Pin
Description Table. The following sections describe
each column.
Column 1. Pin Name
Column 2. Pin Type
Column 3. Input Type (for I and I/O types only)
Prefix Note
have changed, all package prefix variables in this document
are now indicated with an "x".
temperature range corresponding to 0
bient.
x
x
x
x
Table 1: Prefix Identification
1
1
1
proper operation . Stated simply, missing
In this column is a mnemonic that de-
scribes the pin function. Negation of the
signal name (i.e. RESIN) implies that the
signal is active low.
A pin may be either power (P), ground
(G), input only (I), output only (O) or in-
put/output (I/O). Please note that some
pins
A19/S6/ONCE , for example, is normally
an output but functions as an input dur-
ing
A19/S6/ONCE is classified as an input/
output pin.
There are two different types of input
pins on the 80C186EC: asynchronous
and synchronous. Asynchronous pins
require that setup and hold times be met
only to guarantee recognition . Synchro-
nous input pins require that the setup
and hold times be met to guarantee
a setup or hold on an asynchronous pin
will result in something minor (i.e. a timer
count will be missed) whereas missing a
setup or hold on a synchronous pin will
result in system failure (the system will
‘‘lock up’’).
An input pin may also be edge or level
sensitive.
QFP (EIAJ) Extended
PQFP
SQFP
QFP (EIAJ) Commercial
Package
have
Type
reset.
more
Extended/Commercial
Extended/Commercial
For
Temperature
than
˚
Range
C to
this
1
a
function.
70
reason
°
C am-