MC68HC000EI20 Freescale Semiconductor, MC68HC000EI20 Datasheet - Page 72
MC68HC000EI20
Manufacturer Part Number
MC68HC000EI20
Description
IC MPU 16BIT 20MHZ 68-PLCC
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC000IEI16.pdf
(189 pages)
Specifications of MC68HC000EI20
Processor Type
M680x0 32-Bit
Speed
20MHz
Voltage
3.3V, 5V
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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5.4.2 Retrying The Bus Cycle
The assertion of the bus error signal during a bus cycle in which HALT is also asserted by
an external device initiates a retry operation. Figure 5-27 is a timing diagram of the retry
operation. The delayed BERR signal in the MC68010 also initiates a retry operation when
HALT is asserted by an external device. Figure 5-28 shows the timing of the delayed
operation.
5-26
LDS/UDS
FC2-FC0
D15–D0
A23–A1
DTACK
BERR
HALT
R/W
CLK
AS
S0
In the MC68010, if a read-modify-write operation terminates in
a bus error, the processor reruns the entire read-modify-write
operation when the RTE instruction at the end of the bus error
handler returns control to the instruction in error. The
processor reruns the entire operation whether the error
occurred during the read or write portion.
S2
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
READ
Figure 5-27. Retry Bus Cycle Timing Diagram
S4
Freescale Semiconductor, Inc.
For More Information On This Product,
S6
S8
Go to: www.freescale.com
1 CLOCK PERIOD
NOTE
HALT
S0
S2
RETRY
S4
S6
MOTOROLA
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