MC68340AG16VE Freescale Semiconductor, MC68340AG16VE Datasheet - Page 326

• Manufacturer Part Number: MC68340AG16VE
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16VE

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

characters until the shift register is ready to accept more data. When the shift register is
empty, it checks to see if the holding register has a valid character to be sent (TxRDY bit
cleared). If there is a valid character, the shift register loads the character and reasserts
the TxRDY bit in the channel's SR. Writes to the transmitter buffer when the channel's SR
TxRDY bit is clear and when the transmitter is disabled have no effect on the transmitter
buffer. This register can only be written when the serial module is enabled (i.e., the STP
bit in the MCR is cleared).
TB7–TB0—These bits contain the character in the transmitter buffer.
7.4.1.10 INPUT PORT CHANGE REGISTER (IPCR). The IPCR shows the current state
and the change-of-state for the CTSA and CTSB pins. This register can only be read
when the serial module is enabled (i.e., the STP bit in the MCR is cleared).
Bits 7, 6, 3, 2—Reserved
COSB, COSA—Change-of-State
CTSB, CTSA—Current State
MOTOROLA
Starting two serial clock periods after reset, the CTS bits reflect the state of the CTS
pins. If a CTS pin is detected as asserted at that time, the associated COSx bit will be
set, which will initiate an interrupt if the corresponding IECx bit of the ACR register is
enabled.
1 = A change-of-state (high-to-low or low-to-high transition), lasting longer than 25–
0 = The CPU32 has read the IPCR. No change-of-state has occurred. A read of the
1 = The current state of the respective CTS input is negated.
0 = The current state of the respective CTS input is asserted.
50 s when using a crystal as the sampling clock or longer than one or two
periods when using SCLK, has occurred at the corresponding CTS input (MCR
ICCS bit controls selection of the sampling clock for clear-to-send operation).
When these bits are set, the ACR can be programmed to generate an interrupt to
the CPU32.
IPCR also clears the ISR COS bit.
TBA, TBB
Write Only
IPCR
Read Only
RESET:
RESET:
Freescale Semiconductor, Inc.
TB7
7
0
7
0
0
For More Information On This Product,
TB6
6
0
6
0
0
MC68340 USER’S MANUAL
Go to: www.freescale.com
COSB
TB5
5
0
5
0
COSA
TB4
4
0
4
0
TB3
3
0
3
0
0
Supervisor/User
Supervisor/User
TB2
2
0
2
0
0
$713, $71B
CTSB
TB1
1
0
1
U
$714
CTSA
TB0
0
0
0
U
7- 31