IP80C88-2 Intersil, IP80C88-2 Datasheet - Page 9

• Manufacturer Part Number: IP80C88-2
• Description: IC CPU 8/16BIT 5V 8MHZ 40-DIP
• Manufacturer: Intersil

Specifications of IP80C88-2

• Processor Type: 80C88 8/16-Bit
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Bus Operation
The 80C88 address/data bus is broken into three parts: the
lower eight address/data bits (AD0-AD7), the middle eight
address bits (A8-A15), and the upper four address bits (A16-
A19). The address/data bits and the highest four address
bits are time multiplexed. This technique provides the most
efficient use of pins on the processor, permitting the use of
standard 40 lead package. The middle eight address bits are
not multiplexed, i.e., they remain valid throughout each bus
cycle. In addition, the bus can be demultiplexed at the
processor with a single address latch if a standard, non
multiplexed bus is desired for the system.
Each processor bus cycle consists of at least four CLK
cycles. These are referred to as T1, T2, T3 and T4. (See
Figure 5). The address is emitted from the processor during
T1 and data transfer occurs on the bus during T3 and T4. T2
is used primarily for changing the direction of the bus during
read operations. In the event that a “Not Ready” indication is
given by the addressed device, “wait” states (TW) are
inserted between T3 and T4. Each inserted “wait” state is of
the same duration as a CLK cycle. Periods can occur
between 80C88 driven bus cycles. These are referred to as
“idle” states (TI), or inactive CLK cycles. The processor uses
these cycles for internal housekeeping.
DEDICATED
AVAILABLE
INTERRUPT
INTERRUPT
INTERRUPT
RESERVED
POINTERS
POINTERS
POINTERS
(224)
(27)
(5)
9
FIGURE 2. RESERVED MEMORY LOCATIONS
FFFFFH
FFFF0H
3FCH
00CH
3FFH
07FH
084H
080H
014H
010H
008H
004H
000H
1 BYTE INT INSTRUCTION
RESET BOOTSTRAP
TYPE 255 POINTER
TYPE 33 POINTER
TYPE 32 POINTER
TYPE 31 POINTER
PROGRAM JUMP
TYPE 5 POINTER
TYPE 4 POINTER
TYPE 3 POINTER
TYPE 2 POINTER
NON MASKABLE
TYPE 1 POINTER
TYPE 0 POINTER
DIVIDE ERROR
SINGLE STEP
(AVAILABLE)
(AVAILABLE)
(AVAILABLE)
(AVAILABLE)
(RESERVED)
OVERFLOW
16-BITS
80C88
During T1 of any bus cycle, the ALE (Address latch enable)
signal is emitted (by either the processor or the 82C88 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status
information for the cycle may be latched.
Status bits S0, S1, and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to Table 2.
Status bits S3 through S6 are multiplexed with high order
address bits and are therefore valid during T2 through T4.
S3 and S4 indicate which segment register was used to this
bus cycle in forming the address according to Table 3.
S5 is a reflection of the PSW interrupt enable bit. S6 is
always equal to 0.
CS BASE ADDRESS
IP OFFSET
February 22, 2008
FN2949.4