MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 76

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express
17.4.2
The TX eye diagram in
Figure
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage level
of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the
TX UI.
76
T
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
3. A T
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
5. Measured between 20%–80% at transmitter package pins into a test load as shown in
6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
crosslink
any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye diagram shown in
transmitter collected over any 250 consecutive TX UIs. The T
TX jitter budget collected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and
D– line (that is, as measured by a vector network analyzer with 50-Ω probes—see
C
TX
TX-EYE
Symbol
is optional for the return loss measurement.
58) in place of any real PCI Express interconnect +RX component.
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
Transmitter Compliance Eye Diagrams
It is recommended that the recovered TX UI is calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Table 59. Differential Transmitter (TX) Output Specifications (continued)
Crosslink random
timeout
Figure 56
Parameter
is specified using the passive compliance/test measurement load (see
Min
0
Nom
NOTE
—
TX-EYE-MEDIAN-to-MAX-JITTER
Max
1
Unit
ms
This random timeout helps resolve
conflicts in crosslink configuration by
eventually resulting in only one
downstream and one upstream port. See
Note 7.
Figure
Figure 58
58.) Note that the series capacitors
median is less than half of the total
TX-JITTER-MAX
Figure
Figure 58
for both V
Comments
Freescale Semiconductor
56.)
and measured over
= 0.30 UI for the
TX-D+
and V
TX-D–
.