MC68MH360AI33L Freescale Semiconductor, MC68MH360AI33L Datasheet - Page 33

• Manufacturer Part Number: MC68MH360AI33L
• Description: IC MPU QUICC 33MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68MH360AI33L

• Processor Type: M683xx 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

2.1.1 Dual-Ported RAM Base
The MC68MH360’s internal memory is mapped into an 8-Kbyte block of memory, and the
starting address is dictated by the DPRBASE programmed in the MBAR register. For more
detail on the QUICC internal memory structure, see Section 3 of MC68360 Quad
Integrated Communications Controller User’s Manual. The MPC860MH has its internal
memory mapped into a 16-Kbyte block of memory. The ISB programmed in the IMMR
register determines the starting address of this memory block. For more information on the
PowerQUICC internal memory structure, see Section 3 of MPC860 PowerQUICC User’s
Manual. All internal registers are addressed as offsets within the dual-ported RAM;
therefore, all pointers are relative to this base address.
2.1.2 SCC Base and Global Multichannel Parameters
The SCC base points to the start of the parameter RAM for each of the SCCs at 256-byte
intervals. On the MC68MH360, each SCC has 192 bytes of parameter RAM; each SCC on
the MPC860MH has 256 bytes. When the QMC protocol is enabled on an SCC, its
parameter RAM is used to store the global multichannel parameters for all the logical
channels. This area contains parameters and pointers that are common to all channels.
2.1.3 TSATRx/TSATTx Pointers and Time Slot Assignment Table
The time slot assignment table pointers are within the global multichannel parameters.
There are two pointers—Tx_S_PTR for transmit and Rx_S_PTR for receive. The
Rx_S_PTR is normally set to SCC Base + 20; this is the normal location of the receive time
slot assignment table. The Tx_S_PTR is normally set to SCC Base + 60; this is the normal
location of the transmit time slot assignment table. However, if the receiver and the
transmitter have the same mapping for the logical channels, Tx_S_PTR can point to SCC
base + 20 so that Rx and Tx have a common time slot assignment table. Note that if a single
TDM channel is routed to more than one SCC, they may also use just one time slot
assignment table for all SCCs. See Section 2.3, “Multiple SCC Assignment Tables,” for
more information. The time slot assignment table holds one 32-bit entry for each time slot.
It has options for subchanneling, a valid bit, and a logical channel pointer. For 64-channel
support there is only space for one table; therefore, common Rx and Tx parameters will
need to be used unless one of the TSA tables can be accommodated elsewhere in memory,
such as in the parameter RAM area of another SCC. Associated with the Rx/Tx_S_PTR are
the Rx/TxPTR pointers that are maintained by the CPM and point to the current time slot.
As the QMC requires 0xAF bytes of parameter RAM for its
global multichannel parameters, this may cause conflict with
other CPM functionality. For example, when using the
MPC860MH with SCC1 in QMC mode, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Chapter 2. QMC Memory Organization
Go to: www.freescale.com
NOTE
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