DP8344BV National Semiconductor, DP8344BV Datasheet
DP8344BV
Specifications of DP8344BV
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DP8344BV Summary of contents
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... A simple line interface connects the BCP to the communica- tions line The receiver includes an on-chip analog compar- ator suitable for use in a transformer-coupled environment Block Diagram BCP and TRI-STATE are registered trademarks of National Semiconductor Corporation IBM is a registered trademark of International Business Machines Corporation C 1995 National Semiconductor Corporation TL F 9336 ...
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The DP8344B is an enhanced version of the DP8344A exhibiting improved switching performance and additional functionality The device has been been characterized in a number of applications and found compatible replacement for the DP8344A Differences between the ...
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Table of Contents 5 0 DEVICE SPECIFICATIONS 5 1 Pin Description Timing Control Signals Instruction Memory Interface Data Memory Interface Transceiver Interface Remote Interface 5 ...
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Block Diagram of Typical BCP System Biphase Encoding IBM 3270 Message Format Simplified Block Diagram Memory Configuration Effect of Memory Wait States on Timing Register to Register Internal Data Flow Data Memory WRITE Data Flow Data Memory READ Data Flow ...
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List of Illustrations System Block Diagram Showing Details of Line Interface Biphase Encoding 3270 3299 Protocol Framing Format 5250 Protocol Framing Format General Purpose 8-Bit Protocol Framing Format Block Diagram of Transceiver Showing CPU Interface Transmitter Output Timing of Receiver ...
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List of Illustrations Transceiver Timing Analog and DATA-IN Timing Interrupt Timing Control Pin Timing Buffered Read of PC RIC Buffered Read of DMEM Buffered Read of IMEM Latched Read of PC RIC Latched Read of DMEM Latched Read of IMEM ...
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Unsigned Comparison Results Signed Comparison Results Data Memory Wait States Instruction Memory Wait States BIRQ Control Summary ICR Interrupt Mask Bits and Interrupt Priority Interrupt Vector Generation Recommended Crystal Parameters Protocol Mode Definitions Transceiver Interrupts Receiver Interrupts Decode of 3270 ...
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... Communications Processor Introduction The increased demand for computer connectivity has driven National Semiconductor to develop the next generation of special purpose microprocessors The DP8344B is the first example of a ‘‘Communications Processor’’ for the IBM en- vironment It integrates a very fast full function microproc- ...
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Communications Processor Introduction 1 2 INTERNAL ARCHITECTURE INTRODUCTION The DP8344B Biphase Communications Processor (BCP) is divided into three major functional blocks the Transceiver the Central Processing Unit (CPU) and the Remote Inter- face and Arbitration System RIAS Figure ...
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Communications Processor Introduction Simultaneous access to both data and program memory and instruction pipelining greatly enhance the speed per- formance of the BCP making it well suited for real-time pro- cessing The pipeline allows the next instruction to ...
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Communications Processor Introduction 1 4 DATA FLOW The CPU registers are all dual port that is they have sepa- rate input and output paths This arrangement allows a sin- gle register to function as both a source and ...
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Communications Processor Introduction ALU MUX and then placed on the destination bus This data is then stored into the appropriate destination register Figures 1-6b and 1-6c show the data path for data memory accesses For a WRITE operation ...
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CPU Description The CPU is a general purpose 8-bit microprocessor capa- ble of 20 MHz operation It contains a large register set for standard CPU operations and control of the transceiver The reduced instruction set is optimized for ...
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CPU Description (Continued) Registers in the R0–R11 address space are allocated in a manner that minimizes the need to switch banks Main A CPU control and transceiver status Alternate A CPU and transceiver configuration Main B 8 general ...
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CPU Description (Continued) Another control bit in the ACR register is the Clock Out Disable bit COD When COD is asserted the buffered clock output at pin CLK-OUT is tri-stated Interrupt Control Registers The ...
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CPU Description (Continued) Just as TF10 –8 bits get pushed onto the transmitter FIFO when a write to RTR occurs the Receiver FIFO bits RF10–8 in the Transceiver Status Register flect the state of the top word of ...
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CPU Description (Continued) the data stack the next byte pushed will overwrite the first ISP can be read and written to like any other register but after a write the BCP must execute one instruction before reading the ...
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CPU Description (Continued Timer Operation After the desired 16-bit time-out value is written into TRL and TRH the start load and clock selection can be achieved in a single write to ACR A restriction ...
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CPU Description (Continued) 19 ...
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CPU Description (Continued Instruction Set The followng paragraphs introduce the BCP’s architecture by discussing addressing modes and briefly discussing the Instruction Set For detailed explanations and examples of each instruction refer to the Instruction Set ...
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CPU Description (Continued) Indexed Addressing Modes Indexed operands involve one of four possible CPU register pairs referred to as the index registers Figure 2-4 illustrates how the index registers map into the CPU Register Set Note that the ...
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CPU Description (Continued) Integer Arithmetic Instructions The integer arithmetic instructions operate on 8-bit signed (two’s complement) binary numbers Two arithmetic func- tions are supported Add and Subtract Three versions of the Add and Subtract instructions exist operand lator ...
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CPU Description (Continued) Shift and Rotate Instructions The shift and rotate instructions operate on any of the 8-bit CPU registers The BCP supports shift left shift right and rotate operations Table 2-8 lists the shift and rotate instruc- ...
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CPU Description (Continued) mind that the Jcc instruction is just an optional syntax for the conditional JMP instruction The example in Figure 2-5 demonstrates two possible ways to code the conditional relative jump instruction when test- ing for ...
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CPU Description (Continued) The BCP also has a specialized relative jump instruction called relative Jump with Rotate and Mask on source regis- ter JRMK This instruction facilitates the decoding of regis- ter fields often involved in communications processing ...
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CPU Description (Continued) The BCP has one conditional call instruction capable of testing any bit in any currently active CPU register This call only supports absolute instruction addressing Table 2-17 shows the conditional call instruction syntax and operation ...
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CPU Description (Continued) In addition to the above jump call and return program flow instructions the BCP is capable of generating software in- terrupts via the TRAP instruction This instruction generates a call to any one of 64 ...
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CPU Description (Continued CPU FUNCTIONAL DESCRIPTION ALU The BCP provides a full function high speed 8-bit Arithmetic Logic Unit (ALU) with full carry look ahead signed arithme- tic and overflow decision capabilities The ...
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CPU Description (Continued) Several conditions apply to these flags independent of their operation and the way they are calculated These conditions are 1 A flag’s previous state is retained when an instruction has no affect on that flag ...
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CPU Description (Continued) CCS as shown in Figure 2-13 The switch occurs on the falling edge of X1 when CPU-CLK is low CPU-CLK can be changed back to OCLK 2 by writing a one to CCS point at ...
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CPU Description (Continued) Figure 2-14 shows the relationship between CPU-CLK ICLK and IA for a two T-state instruction The rising edge of CPU-CLK generates ICLK at the start of T1 The next falling edge of CPU-CLK increments the ...
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CPU Description (Continued) FIGURE 2-16 Three T-state Data Memory Write Instruction FIGURE 2-17 Three T-state Data Memory Read Instruction 4TR 9336 – 9336– E1 ...
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CPU Description (Continued) When the Four T-state Read mode is selected ( 4TR a second TX state is inserted before T2 and the timing of the read strobe READ is changed such that READ falls one-half T-state after ...
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CPU Description (Continued) FIGURE 2-19 Four T-state Program Control Instruction FIGURE 2-20 Four T-state Two Word Instruction TABLE 2-24 Data Memory Wait States DCR 2–0 Data Wait States 000 0 001 1 010 2 011 3 100 4 ...
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CPU Description (Continued) lowing the instruction after the write to DCR DCR 2–0 to change the number of data wait states will take effect on the next data memory access instruction even if it immediately follows the write ...
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CPU Description (Continued) FIGURE 2-22 Data Memory Read with One Wait State and 4TR FIGURE 2-23 Data Memory Read with Two Wait States and 4TR 9336 – 9336 ...
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CPU Description (Continued) FIGURE 2-24 Two T-state Instruction with Two Wait States FIGURE 2-25 Four T-state Instruction with One Wait State 9336 – 9336 – E7 ...
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CPU Description (Continued) The WAIT pin can also be used to add wait states to BCP instruction execution The CPU will be waited as long as WAIT is low To wait a given instruction WAIT must be as- ...
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CPU Description (Continued) FIGURE 2-28 Three T-state Program Control Instruction WAIT Timing FIGURE 2-29 Four T-state Program Control Instruction WAIT Timing LOCK is another input which affects BCP instruction timing LOCK prevents the BCP from accessing data memory ...
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CPU Description (Continued) FIGURE 2-31 LOCK Timing with One Wait State FIGURE 2-30 LOCK Timing 9336 – 9336 – F4 ...
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CPU Description (Continued) The CPU will be stopped after RESET is asserted low The CPU can be externally controlled by changing the state of the start bit STRT in RIC The CPU starts executing instructions from the current ...
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CPU Description (Continued) 42 ...
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CPU Description (Continued Interrupts The DP8344B has two external and four internal interrupt sources The external interrupt sources are the Non-Maska- ble Interrupt pin NMI and the Bi-directional Interrupt Re- quest pin BIRQ External A ...
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CPU Description (Continued) Internal The internal interrupts consist of the Transmitter FIFO Emp- ty TFE interrupt the Line Turn Around LTA interrupt the Time Out TO interrupt and a user selectable receiver inter- rupt source The receiver interrupt ...
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CPU Description (Continued) A call to the interrupt address is generated when an inter- rupt is detected by the CPU The address for each interrupt is constructed by concatenating the Interrupt Base Register IBR contents with the individual ...
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CPU Description (Continued) FIGURE 2-35 DP8344B Operation with Crystal FIGURE 2-36 DP8344B Operation with External Clock FIGURE 3-1 System Block Diagram Showing Details of the Line Interface 3 0 Transceiver 3 1 TRANSCEIVER ARCHITECTURAL DESCRIPTION The transceiver section ...
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Transceiver (Continued) The transceiver has several modes of operation It can be configured for single line half-duplex operation in which the receiver is disabled while the transmitter is active Alterna- tively both receiver and transmitter can be active ...
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Transceiver (Continued) (c) 3299 Controller Multiplexer Message FIGURE 3-3 3270 3299 Protocol Framing Format FIGURE 3-4 5250 Protocol Framing Format (a) 3270 Single-Byte Message (b) 3270 Multi-Byte Message (a) 5250 Single-Byte Message (b) 5250 Multi-Byte Message 48 TL ...
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Transceiver (Continued) even word parity on the previous 12 bits Following the pari- ty bit 3 biphase ‘‘0’’ fill bits (B0–B2) are transmitted Follow- ing these required fill bits up to 240 additional fill bits can be inserted ...
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Transceiver (Continued) sible for the transmitter and receiver to operate with differ- ent protocols at the same time The protocol mode should only be changed when both transmitter and receiver are inactive If both transmitter and receiver are ...
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Transceiver (Continued) RTR Receive Transmit Register TSR Transceiver Status Register TCR Transceiver Command Register TMR Transceiver Mode Register FIGURE 3-6 Block Diagram of Transceiver Showing CPU Interface KEY TO REGISTERS ATR Auxiliary Transceiver Register NCF Network Command Register ...
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Transceiver (Continued Transmitter The transmitter accepts parallel data from the CPU formats it according to the desired protocol and transmits serial biphase-encoded bit stream A block diagram of the transmitter logic is ...
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Transceiver (Continued Receiver The receiver accepts a serial biphase-encoded bit stream strips off the framing information checks for errors and re- formats the data for parallel transfer to the CPU The block diagram in Figure ...
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Transceiver (Continued) FIGURE 3-8 Timing of Receiver Flags Relative to Incoming Data ister LJMP conditional and LCALL conditional) will result in popping the last location of the FIFO presenting a new word (if present) for future CPU access ...
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Transceiver (Continued Transceiver Interrupts The transceiver has access to 3 CPU interrupt vectors one each for the transmitter and receiver and a third the Line Turn-Around interrupt providing a fast turn around capability between receiver ...
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Transceiver (Continued) lates odd parity on the data byte (B2–B9) and transmits this value for B10 If TCR 2 is high B10 takes the state of TCR 0 Odd Word Parity OWP controls the type of parity calculated ...
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Transceiver (Continued) When formatting a 3299 address frame the procedure is the same as for a 3270 frame with RTR 7 –2 the address to be transmitted The only bit in TCR which has any functional meaning in ...
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Transceiver (Continued) form the 16-bit frame Additional fill bits may be inserted between frames of a multi-frame transmission by loading the fill bit register FBR with the one’s complement of the number of fill bits to be transmitted ...
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Transceiver (Continued Line Interface 3270 Line Interface In the 3270 environment data is transmitted between a con- trol unit and a device via a single coax cable or twisted pair cable ...
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Transceiver (Continued) Legend Transformer D From DP8344 Outputs Legend Transformer Switch Open Twisted Pair Switch Closed Coax FIGURE 3-14 BCP Coax Twisted Pair Front End The cable shield ...
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Transceiver (Continued) high and low The off level corresponds with 0 mA current being driven the high level is nominally 30% and the low level is nominally 30% When these currents ...
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Remote Interface and Arbitration System (RIAS) INTRODUCTION Communication with the BCP is based on the BCP’s ability to share its data memory A microprocessor (or any intelli- gent device) can read and write to any BCP data location ...
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Remote Interface and Arbitration System (RIAS) Signal In Out Pin CMD In 45 LCL Out 31 LOCK In 44 RAE In 46 REM- REM- WR-PEND Out 49 XACK Out 50 WAIT ...
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Remote Interface and Arbitration System (RIAS) arbitration logic determines that the BCP is not using data memory LCL rises relinquishing control of the address and data buses to the RP The remote access can be delayed at most ...
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Remote Interface and Arbitration System (RIAS) Remote Accesses other than to RIC are accomplished with the CMD pin low in conjunction with asserting RAE low along with REM-WR or REM-RD being taken low The type of access performed ...
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Remote Interface and Arbitration System (RIAS) (Continued) (a) Remote Read Timing (RAE 0) e (b) Remote Write Timing (RAE Connectivity FIGURE 4-7 Generic PC Access 9336 – ...
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Remote Interface and Arbitration System (RIAS) (Continued) (a) Remote Read Timing (RAE 0) e (b) Remote Write Timing (RAE Connectivity FIGURE 4-8 Generic IMEM Access 9336 – ...
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Remote Interface and Arbitration System (RIAS) In addition WAIT can delay the rising edge of XACK indefi- nitely One T-state after XACK rises RIC will once again be active on AD Timing is similar for a Remote Write ...
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Remote Interface and Arbitration System (RIAS) FIGURE 4-10 Buffered Write from Remote Processor In both Buffered Write Modes XACK is asserted to wait the RP The Latched Write Mode makes it possible for the RP to write to ...
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Remote Interface and Arbitration System (RIAS) FIGURE 4-12 Minimum BCP Remote Processor Interface The BCP Remote Arbitrator State Machine (RASM) must know what hardware interfaces to the RP in order to time the remote accesses correctly To accomplish ...
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Remote Interface and Arbitration System (RIAS) Programmed wait states delay when WAIT must be assert- ed since programmed wait states are inserted before WAIT is tested to see if any more wait states should be added LOCK prevents ...
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Remote Interface and Arbitration System (RIAS) (Continued) 72 ...
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Remote Interface and Arbitration System (RIAS) (Continued) 73 ...
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Remote Interface and Arbitration System (RIAS) The last possible Memory Selection is Instruction Memory MS1 –0 01 The two possible next states for an IMEM e access depend on if RASM is expecting the low byte or high ...
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Remote Interface and Arbitration System (RIAS) Until a Remote Read is initiated (RAE REM-RD true) the state machine (RASM) loops in state RS A1 Read is initiated and LOR is set high RASM will move to state RS ...
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Remote Interface and Arbitration System (RIAS) (Continued) 76 ...
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Remote Interface and Arbitration System (RIAS) (Continued) 77 ...
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Remote Interface and Arbitration System (RIAS) On the next clock the state machine will enter RS will return low The A bus (and AD bus if the access is to data memory) remains in TRI-STATE for the first ...
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Remote Interface and Arbitration System (RIAS) (Continued) 79 ...
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Remote Interface and Arbitration System (RIAS) the last action of the remote access before moving switch HIB and increment the PC if the high byte was written In RS LCL goes low while A ...
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Remote Interface and Arbitration System (RIAS) (Continued) 81 ...
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Remote Interface and Arbitration System (RIAS) state and A and AD continue to be tri-stated This allows the Remote Processor to drive the Data Memory address and data buses for the write Since DMEM is subject to wait ...
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Remote Interface and Arbitration System (RIAS) (Continued) 83 ...
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Remote Interface and Arbitration System (RIAS) (Continued) 84 ...
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Remote Interface and Arbitration System (RIAS Latched Write This mode executes a write without waiting the Remote Processor XACK isn’t normally taken low The complete flow chart for the Latched Write mode is shown in ...
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Remote Interface and Arbitration System (RIAS) (Continued) 86 ...
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Remote Interface and Arbitration System (RIAS) (Continued) 87 ...
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Remote Interface and Arbitration System (RIAS) The BCP is now shown executing a local memory write with remote data still pending in the latch At the end of this instruction the BCP begins executing a series of internal ...
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Remote Interface and Arbitration System (RIAS) (a) This timing diagram shows two remote accesses within one T-state The first set of arrows shows the BCP sampling a valid remote read The next time the BCP samples the validity ...
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Remote Interface and Arbitration System (RIAS) (a) This timing diagram shows the second remote access violating rest time The first set of arrows shows the BCP sampling a valid remote write The second set of arrows (1 T-state ...
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Remote Interface and Arbitration System (RIAS) (a) This timing diagram shows a remote access violating remote rest time The first set of arrows shows the BCP sampling the value of CMD when WR-PEND rises If a remote access ...
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Remote Interface and Arbitration System (RIAS) (c) This timing diagram shows a remote access setting up in time for WR-PEND rising to latch in the proper value of CMD The only set of arrows shows the BCP sampling ...
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Device Specifications 5 1 PIN DESCRIPTIONS Reset Signal In Out Pin State TIMING CONTROL SIGNALS Out 34 X1 CLK-OUT Out 35 X1 X-TCLK WAIT ...
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Device Specifications Reset Signal In Out Pin State INSTRUCTION MEMORY INTERFACE (Continued) Instruction Address Bus (Continued) IA9 Out 64 0 IA8 Out 65 0 IA7 Out 68 0 IA6 Out 69 0 IA5 Out 70 ...
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Device Specifications Reset Signal In Out Pin State DATA MEMORY INTERFACE (Continued) Timing Control ALE Out 28 0 READ Out 29 1 WRITE Out TRANSCEIVER INTERFACE DATA- ...
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... Device Specifications 5 2 ABSOLUTE MAXIMUM RATINGS (Notes 1 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Input Diode Current DC Output Voltage ( OUT DC Output Current per Pin (I ...
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Device Specifications (Continued SWITCHING CHARACTERISTICS The following specifications apply for Definitions The timing specifications for the BCP are provided in the following ...
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Device Specifications (Continued) Note for t and PZL PLZ S GND for t and PZH PHZ S Open for push pull outputs e 1 Note ...
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Device Specifications TABLE 5-3 Data Memory Read Timing (Note 1) Symbol ID Parameter t 1 ALE High W-ALE (Data Address) Valid to ALE Falling PD-AAD-ALE t 3 ALE Falling to AD (Data Address) Invalid ...
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TABLE 5-4 Data Memory Write Timing (Note Device Specifications (Continued) TABLE 5-4 Data Memory Write Timing (Note 1) Symbol ID Parameter t 1 ALE High W-ALE (Data Address) Valid to ALE Falling PD-AAD-ALE ...
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Device Specifications (Continued) TABLE 5-5 Instruction Memory Read Timing (Note 1) Symbol ID Parameter t 1 Instruction Memory Read Time ACC Invalid to I Invalid H-IA ICLK Rising to IA Invalid PD-ICLK-IA t ...
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Device Specifications (Continued) Symbol Period (Note 2) T- CLK-OUT (Note 2) PD-X1- CLK-OUT Rising to ICLK Rising PD-CO-ICLKr t 4 CLK-OUT Rising to ICLK Falling (Note 3) PD-CO-ICLKf ...
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Device Specifications (Continued) TABLE 5-7 Transceiver Timing (Note 1) Symbol Rising to TX-ACT Rising Falling PD-X1- X-TCLK Rising to TX-ACT Rising Falling PD-XTCLK- DATA-OUT DATA-DLY Valid to TX-ACT Rising PD-DODD-TA ...
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Device Specifications (Continued) TABLE 5-8 Analog and DATA-IN Timing (Note 1) Symbol ID Parameter t 1 DATA-IN Data Half Bit Width W-DI- DATA-IN Data Full Bit Width W-DI- Analog Data Half Bit Width W-AI-hb ...
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Device Specifications (Continued) Symbol NMI Falling before CLK-OUT Falling SU-NMI- NMI Hold after CLK-OUT Falling H-NMI- BIRQ (Input) Falling before CLK-OUT Falling SU-BQ- ICLK Rising to BIRQ (Output) Rising ...
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Device Specifications Symbol ID Parameter t 1 RESET Low W-RST t 2 RESET Rising to ICLK Rising PD-RST-ICLK t 3 WAIT Low after ALE High to Extend Cycle SU-ALE- WAIT Rising after ALE Falling (Note 2) ...
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Device Specifications (Continued) (a) Reset Timing (b) BCP Access WAIT Timing (c) LOCK Timing (d) Instruction WAIT Timing FIGURE 5-10 Control Pin Timing 107 TL F 9336– 9336 – 9336 – 64 ...
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TABLE 5-11 Buffered Read of PC RIC (Note Device Specifications (Continued) TABLE 5-11 Buffered Read of PC RIC (Note 1) Symbol RAE REM-RD Falling before CLK-OUT Rising SU-RRR- RAE REM-RD Rising after ...
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Device Specifications (Continued) TABLE 5-12 Buffered Read of DMEM (Note 1) Symbol RAE REM-RD Falling before CLK-OUT Rising SU-RRR- RAE REM-RD Rising after XACK Rising (Note 2) H-RRR CMD Valid before ...
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Device Specifications (Continued) TABLE 5-13 Buffered Read of IMEM (Note 1) Symbol RAE REM-RD Falling before CLK-OUT Rising SU-RRR- RAE REM-RD Rising after XACK Rising (Note 2) H-RRR CMD Valid before ...
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Device Specifications (Continued) TABLE 5-14 Latched Read of PC RIC (Note 1) Symbol RAE REM-RD Falling before CLK-OUT Rising SU-RRR- RAE REM-RD Rising after XACK Rising H-RRR CMD Valid before RAE ...
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Device Specifications (Continued) TABLE 5-15 Latched Read of DMEM (Note 1) Symbol RAE REM-RD Falling before CLK-OUT Rising SU-RRR- RAE REM-RD Rising after XACK Rising H-RRR CMD Valid before RAE REM-RD ...
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Device Specifications (Continued) TABLE 5-16 Latched Read of IMEM (Note 1) Symbol RAE REM-RD Falling before CLK-OUT Rising SU-RRR- RAE REM-RD Rising after XACK Rising H-RRR CMD Valid before RAE REM-RD ...
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Device Specifications (Continued) TABLE 5-17 Slow Buffered Write of PC RIC (Note 1) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after XACK Rising (Note 2) H-RRW CMD ...
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Device Specifications (Continued) TABLE 5-18 Slow Buffered Write of DMEM (Note 1) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after XACK Rising (Note 2) H-RRW CMD Valid ...
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Device Specifications (Continued) TABLE 5-19 Slow Buffered Write of IMEM (Notes 1 2) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after XACK Rising (Note 3) H-RRW CMD ...
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Device Specifications (Continued) 117 ...
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Device Specifications (Continued) TABLE 5-20 Fast Buffered Write of RIC PC (Note 1) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after XACK Rising H-RRW CMD Valid before ...
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Device Specifications (Continued) TABLE 5-21 Fast Buffered Write of DMEM (Note 1) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after XACK Rising H-RRW CMD Valid before RAE ...
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Device Specifications (Continued) TABLE 5-22 Fast Buffered Write of IMEM (Notes 1 2) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after XACK Rising H-RRW CMD Valid before ...
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Device Specifications (Continued) FIGURE 5-22 Fast Buffered Write of IMEM 121 TL F 9336 – 76 ...
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Device Specifications (Continued) TABLE 5-23 Latched Write of PC RIC (Note 1) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after CLK-OUT Rising (Note 2) H-RRW- RAE REM-WR ...
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Device Specifications TABLE 5-24 Latched Write of DMEM (Note 1) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after CLK-OUT Rising (Note 2) H-RRW- RAE REM-WR Rising after ...
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Device Specifications TABLE 5-25 Latched Write of IMEM (Notes 1 2) Symbol RAE REM-WR Falling before CLK-OUT Rising SU-RRW- RAE REM-WR Rising after CLK-OUT Rising (Note 3) H-RRW- RAE REM-WR Rising ...
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Device Specifications (Continued) FIGURE 5-25 Latched Write of IMEM 125 TL F 9336 – 79 ...
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Device Specifications (Continued) TABLE 5-26 Remote Rest Time (Note 1) Symbol REM-RD Rising before CLK-OUT Rising SU-BR-RR-CO (Buffered Read Mode CLK-OUT Rising after REM-RD Rising to REM-RD H-BR or REM-WR Falling (Buffered Read ...
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Device Specifications (Continued) (a) REM-RD Rest Time (Buffered Read Mode) (b) REM-RD Rest Time (Latched Read Mode) (c) REM-WR Rest Time (Slow Buffered Write Mode) (d) REM-WR Rest Time (Fast Buffered Write Mode) (e) REM-WR Rest Time (Latched ...
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Device Specifications (f) WR-PEND Rising (Latched Write Mode) FIGURE 5-26 Remote Rest Time (Continued) TABLE 5-27 Remote Interface WAIT Timing (Note 1) Symbol WAIT Falling after LCL Rising to Extend Cycle SU-WT-LCL (Buffered Read Latched ...
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Device Specifications TABLE 5-27 Remote Interface WAIT Timing (Note 1) (Continued) Symbol WAIT Rising after READ Falling H-WT-RD (Buffered Read and Latched Read) (Note WAIT Rising after WRITE Falling (Slow Buffered Write ...
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Device Specifications TABLE 5-28 Wait Timing After Remote Access (Note 1) Symbol LCL Falling (Data Address) Valid PD-LCL-AAD t LCL Falling (Data Address) Valid PD-LCL-AAD-BR for Buffered Read of ...
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Reference Section 6 1 INSTRUCTION SET REFERENCE The Instruction Set Reference section contains detailed in- formation on the syntax and operation of each BCP instruc- tion The instructions are arranged in alphabetical order by mnemonic for easy access ...
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Reference Section (Continued) In the ‘‘Blocked If’’ structure if the condition is met then all the operations between the ‘‘If’’ statement and the ‘‘End if’’ statement are performed ‘‘Blocked If’’ structure If condition then operation operation etc End ...
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Reference Section (Continued) FIGURE 6-1 Instruction-Memory Bus Timing for 2 T-state Instructions (No Instruction Wait States IW1–0 FIGURE 6-2 Instruction-Memory Bus Timing for 3 T-state Instructions (No Instruction Wait States IW1– 9336– CPU Running ...
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Reference Section (Continued) FIGURE 6-3 Instruction-Memory Bus Timing for (2 (No Instruction Wait States IW1–0 FIGURE 6-4 Instruction-Memory Bus Timing for 4 T-state Instructions (No Instruction Wait States IW1–0 2) T-state Instructions a 00 CPU Running at Full ...
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Reference Section (Continued) FIGURE 6-5 Instruction Data Memory Bus Timing for Data Memory Read (No Instruction or Data Memory Wait States CPU Running at Full Speed CCS FIGURE 6-6 Instruction Data Memory Bus Timing for Data Memory Read ...
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Reference Section (Continued) FIGURE 6-7 Instruction Data Memory Bus Timing for Data Memory Write (No Instruction or Data Memory Wait States CPU Running at Full Speed CCS ADCA Add with Carry and Accumulator Syntax ADCA Rs Rd register ...
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Reference Section (Continued) ADD Add Immediate Syntax ADD n rsd immediate limited register Affected Flags Description Adds the immediate value n to the register rsd and places the result back into the register rsd ...
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Reference Section (Continued) ANDA And with Accumulator Syntax ANDA Rs Rd register register ANDA Rs mIr register indexed Affected Flags N Z Description Logically ANDs the source register Rs to the active accumu- lator and places the result ...
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Reference Section (Continued) CALL Unconditional Relative Call Syntax CALL n immediate Affected Flags None Description Pushes the Program Counter the ALU flags the Global In- terrupt Enable bit GIE and the current register bank selec- tions onto the ...
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Reference Section (Continued) CPL Complement Syntax CPL Rsd register Affected Flags N Z Description Logically complements the contents of the register Rsd placing the result back into that register Example Load the fill-bit count passed from the host ...
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Reference Section (Continued) JMP Conditional Relative Jump Jcc Syntax JMP immediate Jcc n immediate (optional syntax) Affected Flags None Description Conditionally transfers control to the instruction at the mem- ory address calculated by adding the ...
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Reference Section (Continued) JMP Unconditional Relative Jump Syntax JMP n immediate JMP Rs register Affected Flags None Description Unconditionally transfers control to the instruction at the memory address calculated by adding the contents of the Program Counter to ...
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Reference Section (Continued) JRMK Relative Jump with Rotate and Mask on Register Syntax JRMK register Affected Flags None Description Transfers control to the instruction at the memory address calculated by adding the contents of the ...
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Reference Section (Continued) LCALL Conditional Long Call Syntax LCALL register absolute Affected Flags None Description If the bit in position p of register Rs is equal to the bit s then push the Program ...
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Reference Section (Continued) LJMP Conditional Long Jump Syntax LJMP register absolute Affected Flags None Description Conditionally transfers control to the instruction at the abso- lute memory address nn if the bit in position p ...
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Reference Section (Continued) MOVE Move Data Memory Syntax MOVE mIr Rd indexed register MOVE register-relative register a MOVE immediate-relative limited register a Affected Flags None Description Moves a data memory byte into ...
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Reference Section (Continued) MOVE Move Immediate Syntax MOVE n rd immediate limited register MOVE n Ir immediate indexed Affected Flags None Description Moves the immediate value n into the destination specified The destination may be either a register ...
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Reference Section (Continued) MOVE Move Register Syntax MOVE Rs Rd register register MOVE Rs mIr register indexed MOVE register register-relative a MOVE limited register immediate-relative a Affected Flags None Description Moves the ...
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Reference Section (Continued Immediate Syntax OR n rsd immediate limited register Affected Flags N Z Description Logically ORs the immediate value n to the register rsd and places the result back into the register rsd Note ...
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Reference Section (Continued) RETF Conditional Return Rcc Syntax RETF Rcc g rf (optional syntax) Affected Flags then and V e Description Conditionally returns control to the last instruction ...
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Reference Section (Continued) RET Unconditional Return Syntax RET g rf Affected Flags then and V e Description Unconditionally returns control to the last instruction ad- dress pushed onto the internal Address Stack ...
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Reference Section (Continued) SBCA Subtract with Carry and Accumulator Syntax SBCA Rs Rd register register SBCA Rs mIr register indexed Affected Flags Description Subtracts the active accumulator and the carry flag from the source ...
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Reference Section (Continued) SHR Shift Right Syntax SHR Rsd b register Affected Flags Description Shifts the contents of the register Rsd b bits to the right and places the result back into that register Zeros ...
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Reference Section (Continued) SUBA Subtract with Accumulator Syntax SUBA Rs Rd register register SUBA Rs mlr register indexed Affected Flags Description Subtracts the active accumulator from the source register Rs and places the result ...
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Reference Section (Continued) XOR Exclusive OR Immediate Syntax XOR n rsd immediate limited register Affected Flags N Z Description Logically exclusive ORs the immediate value n to the regis- ter rsd and places the result back into the ...
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Reference Section (Continued) TABLE 6-2 Instructions Versus T-states Affected Flags and Bus Timing Affected Instruction T-states ADCA ADCA Rs mlr ADD n rsd ...
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Reference Section (Continued) TABLE 6-3 Instruction Opcodes Hex Opcode 0000 –0FFF Opcode 1000 –1FFF Opcode 2000 –2FFF Opcode ...
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Reference Section (Continued) TABLE 6-3 Instruction Opcodes (Continued) Hex Opcode 8800 –8BFF Opcode n 7– 8C00 –8DFF Opcode 15 0000–FFFF ...
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Reference Section (Continued) TABLE 6-3 Instruction Opcodes (Continued) Hex Opcode A600 –A7FF Opcode A800 –A9FF Opcode ...
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Reference Section (Continued) TABLE 6-3 Instruction Opcodes (Continued) Hex Opcode C000 –C1FF Opcode C200 –C3FF Opcode ...
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Reference Section (Continued) TABLE 6-3 Instruction Opcodes (Continued) Hex Opcode CD00 –CD60 Opcode CD80 –CD9F Opcode 15 CE00 ...
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Reference Section (Continued) TABLE 6-3 Instruction Opcodes (Continued) Hex Opcode E000–E3FF Opcode E400–E7FF Opcode E800 –EBFF ...
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Reference Section (Continued REGISTER SET REFERENCE The register set reference contains detailed information on the bit definitions of all special function registers that are address- able in the CPU This reference section presents the information in ...
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Reference Section (Continued Bit Index (Continued) An alphabetical listing of all status control bits in the CPU-addressable special function registers with a brief summary of function Detailed definitions are provided in Section ...
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Reference Section (Continued) ATR AUXILIARY TRANSCEIVER REGISTER Alternate R2 read write AT7 AT6 AT5 AT4 AT3 AT2 AT7 –0 Auxiliary Transceiver In 5250 protocol modes bits 2–0 define the receive station ad- ...
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Reference Section (Continued) DCR DEVICE CONTROL REGISTER Alternate R0 read write CCS TCS1 TCS0 IW1 IW0 DW2 CCS CPU Clock Select Selects CPU clock fre- quency OCLK represents the frequency of the ...
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Reference Section (Continued) ECR ERROR CODE REGISTER Alternate R4 with SEC high read only rsv rsv rsv OVF PAR IES OVF Receiver oVerFlow Set when the receiver has processed 3 words and ...
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Reference Section (Continued) IBR INTERRUPT BASE REGISTER Alternate R1 read write IV15 IV14 IV13 IV12 IV11 IV10 IV15 –8 High byte of interrupt and Interrupt Vector trap vectors Further information Section 2 ...
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Reference Section (Continued) ISP INTERNAL STACK POINTER Main R30 read write ASP3 ASP2 ASP1 ASP0 DSP3 DSP2 DSP1 DSP0 ASP3 –0 Address Stack Pointer Input output port of the address stack pointer ...
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Reference Section (Continued) RTR RECEIVE TRANSMIT REGISTER Alternate R4 read write RTF7 RTF6 RTF5 RTF4 RTF3 RTF2 RTF1 RTF0 RTF7–0 Receive Transmit FIFO’s port to the least significant eight bits of receive ...
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Reference Section (Continued) TMR TRANSCEIVER MODE REGISTER Alternate R7 read write TRES LOOP RPEN RIN TIN PS2 TRES Transceiver RESet Resets transceiver when high Transceiver can also be reset by RESET without ...
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Reference Section (Continued) TRL TIMER REGISTER LOW Main R28 read write TM7 TM6 TM5 TM4 TM3 TM2 TM7 –0 TiMer Input output port of low byte of timer Further information Section 2 ...
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Reference Section (Continued Bit Definition Tables The following tables describe the location and function of all control and status bits in the various BCP addressable special function registers The Remote Interface Configuration register included 6 ...
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Reference Section (Continued Bit Definition Tables (Continued) The following tables describe the location and function of all control and status bits in the various BCP addressable special function registers The Remote Interface Configuration register included ...
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Reference Section (Continued Bit Definition Tables (Continued) The following tables describe the location and function of all control and status bits in the various BCP addressable special function registers The Remote Interface Configuration register included ...
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Reference Section (Continued Bit Definition Tables (Continued Transceiver (Continued) Table includes control and status bits only It does not include definitions of bit fields provided for the formatting (de-formatting) data frames ...
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Reference Section (Continued Bit Definition Tables (Continued Transceiver (Continued) Table includes control and status bits only It does not include definitions of bit fields provided for the formatting (de-formatting) data frames ...
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Reference Section (Continued Bit Definition Tables (Continued Transceiver (Continued) Table includes control and status bits only It does not include definitions of bit fields provided for the formatting (de-formatting) data frames ...
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... THIRD PARTY SUPPLIERS The following section is intended to make the DP8344 Cus- tomer aware of products supplied by companies other than National Semiconductor that are available for use in devel- oping DP8344 systems While National Semiconductor has supported these ventures and has become familiar with ...
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Reference Section (Continued) Scope are single PC expansion cards that can record de- code and display activity on the 3270 coax and 5250 twinax line respectively These devices also allow the play back of the recorded controller information ...
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Reference Section (Continued) 4TR in ACR When a one is written to this bit all subse- quent data memory read operations expand to 4 T-states with an extra one-half T-state between the falling edge of ALE and the ...
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... Dedicated hardware for shifting and rotat- ing BCP An abbreviation for Biphase Communications Proc- essor the National Semiconductor DP8344 biphase In this communications signal encoding tech- nique the data is divided into discrete bit time intervals de- noted by a transition in the center of the bit time This tech- ...
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Reference Section (Continued) line hold The act of driving the transmission line during 5250 transmissions at the end of a message to allow the receivers to unsync This insures that the receivers will not see line noise as ...
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... Hong Kong Ltd 49) 0-180-530 85 86 13th Floor Straight Block a Ocean Centre 5 Canton Rd 49) 0-180-530 85 85 Tsimshatsui Kowloon a Tel ( 49) 0-180-532 78 32 Hong Kong a 49) 0-180-532 93 58 Tel (852) 2737-1600 a Tel ( 49) 0-180-534 16 80 Fax (852) 2736-9960 a National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 ...