DP8344BV National Semiconductor, DP8344BV Datasheet - Page 15

• Manufacturer Part Number: DP8344BV
• Description: IC BIPHASE COMM PROCESSR 84-PLCC
• Manufacturer: National Semiconductor

Specifications of DP8344BV

• Processor Type: 8-Bit RISC
• Speed: 20MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: *DP8344BV

2 0 CPU Description
Another control bit in the ACR register is the Clock Out
Disable bit COD When COD is asserted the buffered
clock output at pin CLK-OUT is tri-stated
2 1 1 3 Interrupt Control Registers
The configuration bank (Alternate Bank A) includes an Inter-
rupt Base Register
interrupt and trap vector addresses Thus the interrupt vec-
tor table can be located in any 256 byte page of the 64k
range of instruction addresses The interrupt base is nor-
mally initialized once on reset before interrupts are enabled
or any traps are executed Since NMI is nonmaskable and
may occur before IBR is initialized the power-up reset
value of IBR (00h) should be used to accommodate NMI
during initialization In other words if NMI is used in the
system the absolute address 001Ch (the NMI vector)
should contain a jump to an NMI service routine
The Interrupt Control Register
masks IM4–0 for each of the maskable interrupts The
Global Interrupt Enable bit GIE located in ACR works
in conjunction with these individual masks to control each of
the maskable interrupts
The external pin called BIRQ is a Bidirectional Interrupt
ReQuest BIRQ is defined as an input or an output by the
Bidirectional Interrupt Control bit
functions as BIRQ’s interrupt mask if BIRQ is an input as
defines by BIC
Section 2 2 3 Interrupts provides a further description of
these registers
2 1 1 4 Timer Registers
The timer block interfaces with the CPU via two registers
TimeR Low byte
which form the input output ports to the timer Writing to
ly of a 16-bit time-out value into two holding registers The
word stored in the holding registers is the value that the
timer will be loaded with via TLD Also the timer will auto-
matically reload this word upon timing out Reading TRL
and TRH provides access to the count down status of the
timer
Control of timer operation is maintained via three bits in the
Auxiliary Control Register ACR
in ACR
rent value When low the timer stops and the timer interrupt
is cleared Timer Load TLD
control of the timer After writing the desired values into
word in the holding registers into the timer and initialize the
timer clock to zero in preparation to start counting Upon
completing the load operation
cleared Timer Clock Selection TCS bit 5 in ACR deter-
mines the clock frequency of the timer count down When
low the timer divides the CPU clock by sixteen to form the
clock for the down counter When TCS is high the timer
divides the CPU clock by two The input clock to the timer is
the CPU clock and should not be confused with the oscilla-
tor clock OCLK The rate of the CPU clock will be either
equal to OCLK or one-half of OCLK depending on the value
of bit 7 in the Device Control Register
IM3 controls the output state of BIRQ
TST allows the timer to start counting down from its cur-
TRL and TRH stores the low and high byte respective-
TRL and TRH writing a one to TLD will load the 16-bit
is the start stop control bit Writing a one to
When BIC defines BIRQ as an output
TRL
IBR
which defines the high byte of all
and TimeR High byte
bit 6 in ACR
(Continued)
ICR
Timer STart TST bit 7
TLD
BIC
provides individual
DCR
in ACR
is automatically
is the load
TRH
IM3
15
When the timer reaches a count of zero the timer interrupt
is generated the Time Out flag TO (bit 7 in the Condition
Code Register CCR ) goes high and the timer reloads the
16-bit word stored in the holding registers to recycle through
a count down The timer interrupt and TO can be cleared
by either writing a one to TO in CCR or stopping the
timer by writing a zero to TST in ACR
2 1 2 Timer for more information on the timer operation
2 1 1 5 Transceiver Registers
Two registers in the Alternate A bank initialize transceiver
functions The Auxiliary Transceiver Register ATR
fies a station address used by the address recognition logic
within the transceiver when using the non-promiscuous
5250 and 8-bit protocol modes In 5250 modes
defines how long the TX-ACT pin stays asserted after the
end of a transmitted message The Fill Bit Register
specifies the number of optional fill bits inserted between
frames in a multiframe 5250 message
These bits determine the receiver interrupt source selection
The source may be either Receiver FIFO Full Data Avail-
able or Receiver Active
The Receive Transmit Register
port to both the transmitter and receiver FIFO’s It appears
to the BCP CPU like any other register The RTR register
provides the least significant eight bits of data in both re-
ceived and transmitted messages
The Transceiver Mode Register
to set the configuration of the transceiver As long as the
Transceiver RESet bit TRES is high the transceiver re-
mains in reset Internal LOOP-back operation of the trans-
ceiver can be selected by asserting LOOP
ENable bit RPEN allows the receiver to be active at the
same time as the transmitter When the Receiver INvert bit
Transmitter INvert bit TIN is analogous to RIN except it
is for the transmitter The protocol that the transceiver is
using is selected with the Protocol Select bits PS2 –0
The Transceiver Command Register
workings of the transmitter To generate 5 5 line quiesce
pulses at the start of a transmission rather than 5 the Ad-
vance Transmitter Active bit ATA must be set high Parity
is automatically generated on a transmission and the Odd
Word Parity bit
even or odd Bits 2– 0 of TCR make up part of the Trans-
mitter FIFO TF10– 8 along with RTR
is made to RTR
the FIFO with the 8 bits written to RTR
Other bits in TCR control the operation of the on-chip
receiver The number of line quiesce bits the receiver must
detect to recognize a valid message is determined by the
Receive Line Quiesce bit RLQ The BCP has its own inter-
nal analog comparator but an off-chip one may be connect-
ed to DATA-IN The receiver source is determined by the
Select Line Receiver bit SLR To view transceiver errors
in the Error Code Register
Alternate Bank B R4 is remapped from RTR to ECR so
that ECR can be read
RIN is set all data sent to the receiver is inverted The
SEC bit in TCR must be set high When SEC is high
ICR contains the Receiver Interrupt Select bits RIS1 0
OWP
TF10 – 8 are automatically pushed on
determines whether that parity is
ECR
RTR
TMR
the Select Error Codes
TCR
is the input output
contains bits used
Whenever a write
Refer to Section
The RePeat
controls the
ATR also
FBR
speci-