UDA1384H/N1,557 NXP Semiconductors, UDA1384H/N1,557 Datasheet - Page 16

• Manufacturer Part Number: UDA1384H/N1,557
• Description: IC AUDIO CODEC 44-QFP
• Manufacturer: NXP Semiconductors
• Type: Audio Codecr

Specifications of UDA1384H/N1,557

• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 5 / 6
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 98 / 110 (Differential), 98 / 110 (Single-Ended)
• Voltage - Supply, Analog: 2.7 V ~ 3.6 V
• Voltage - Supply, Digital: 2.7 V ~ 3.6 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-MQFP, 44-PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3450; 935274756557; UDA1384H

Philips Semiconductors
9397 750 14366
Product data sheet
9.2 Device addressing
9.3 Register addressing
The data transfer mode is characterized by signal L3MODE = HIGH and is used to
transfer one or more bytes representing a register address, instruction or data.
Basically, two types of data transfers can be defined:
The device address consists of one byte with:
Table 13:
After sending the device address (including DOM bits), indicating whether the information
is to be read or written, one data byte is sent using bit 0 to indicate whether the
information will be read or written and bits 1 to 7 for the destination register address.
Basically, there are 3 methods for register addressing:
DOM
1. Addressing for write data: bit 0 is logic 0 indicating a write action to the destination
2. Addressing for prepare read: bit is logic 1, indicating that data will be read from the
3. Addressing for data read action. Here, the device returns a register address prior to
•
•
•
•
Write action: data transfer to the device
Read action: data transfer from the device.
Data Operating Mode (DOM) bits 0 and 1 representing the type of data transfer (see
Table
Address bits 2 to 7 representing a 6-bit device address. The address of the UDA1384
is 01 0100 (bits 2 to 7).
register, followed by bits 1 to 7 indicating the register address (see
register (see
sending data from that register. When bit 0 is logic 0, the register address is valid;
when bit 0 is logic 1, the register address is invalid (see
13)
Selection of data transfer
Bit 1
0
0
1
1
Figure
Rev. 02 — 17 January 2005
12).
Bit 0
0
1
0
1
Multichannel audio coder-decoder
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Figure
Transfer
not used
not used
write data or prepare read
read data
12).
UDA1384
Figure
11).
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