TP3064J National Semiconductor, TP3064J Datasheet - Page 2

• Manufacturer Part Number: TP3064J
• Description: IC FILTER MONO SRL COMBO 20DIP
• Manufacturer: National Semiconductor
• Type: PCM Codec/Filterr

Specifications of TP3064J

• Data Interface: Serial
• Resolution (bits): 8 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 20-CDIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *TP3064J

Connection Diagrams
Pin Description
VPO
GNDA
VPO
VPI
VF
V
FS
D
BCLK
CLKSEL
MCLK
PDN
Symbol
CC
R
R
R
O
b
a
R
R
The non-inverted output of the receive power
amplifier
Analog ground All signals are referenced to
this pin
The inverted output of the receive power
amplifier
Inverting input to the receive power amplifier
Analog output of the receive filter
Positive power supply pin V
Receive frame sync pulse which enables
BCLK
8 kHz pulse train See Figures 2 and 3 for
timing details
Receive data input PCM data is shifted into
D
The bit clock which shifts data into D
the FS
to 2 048 MHz Alternatively may be a logic
input which selects either
1 536 MHz 1 544 MHz or 2 048 MHz for
master clock in synchronous mode and
BCLK
directions (see Table I)
Receive master clock Must be 1 536 MHz
1 544 MHz or 2 048 MHz May be
asynchronous with MCLK
synchronous with MCLK
performance When MCLK
continuously low MCLK
internal timing When MCLK
continuously high the device is powered
down
R
following the FS
R
X
R
is used for both transmit and receive
to shift PCM data into D
leading edge May vary from 64 kHz
Dual-In-Line Package
Top View
Function
R
leading edge
X
X
X
is selected for all
for best
R
CC
but should be
R
is connected
is connected
e a
R
FS
5V
TL H 5070– 2
R
R
g
after
is an
5%
2
Symbol
MCLK
BCLK
D
FS
TS
ANLB
GS
VF
VF
V
BB
X
X
X
X
X
X
I
I
b
a
X
X
Order Number TP3064WM or TP3067WM
Order Number TP3064N or TP3067N
Order Number TP3064V or TP3067V
Order Number TP3064J or TP3067J
Transmit master clock Must be 1 536 MHz
1 544 MHz or 2 048 MHz May be
asynchronous with MCLK
performance is realized from synchronous
operation
The bit clock which shifts out the PCM data
on D
but must be synchronous with MCLK
The TRI-STATE PCM data output which is
enabled by FS
Transmit frame sync pulse input which
enables BCLK
D
and 3 for timing details
Open drain output which pulses low during
the encoder time slot
Analog Loopback control input Must be set
to logic ‘0’ for normal operation When pulled
to logic ‘1’ the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPO
output of the receive power amplifier
Analog output of the transmit input amplifier
Used to externally set gain
Inverting input of the transmit input amplifier
Non-inverting input of the transmit input
amplifier
Negative power supply pin V
X
FS
X
See NS Package M20B
See NS Package N20A
See NS Package V20A
See NS Package J20A
Plastic Chip Carrier
X
May vary from 64 kHz to 2 048 MHz
is an 8 kHz pulse train see Figures 2
Top View
X
X
to shift out the PCM data on
Function
R
Best
BB
eb
5V
TL H 5070 – 6
X
a
g
5%