SC18IS600IBS,151 NXP Semiconductors, SC18IS600IBS,151 Datasheet
SC18IS600IBS,151
Specifications of SC18IS600IBS,151
935286452151
SC18IS600IBS-S
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SC18IS600IBS,151 Summary of contents
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SC18IS600/601 SPI to I Rev. 05 — 28 July 2008 1. General description The SC18IS600/601 is designed to serve as an interface between the standard SPI of a host (microcontroller, microprocessor, chip set, etc.) and the serial I the host ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name Description SC18IS600IPW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SC18IS601IPW SC18IS600IBS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 4. Block diagram ...
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... NXP Semiconductors SC18IS601 CONTROL RESET MISO MOSI SCLK CS INT INTERRUPT CONTROL external clock input OSCILLATOR (CLKIN) Fig 2. Block diagram of SC18IS601 SC18IS600_601_5 Product data sheet LOGIC SPI LOGIC Rev. 05 — 28 July 2008 SC18IS600/601 SPI C-BUS BUFFER CONTROLLER GENERAL PURPOSE I/Os 002aab784 © NXP B.V. 2008. All rights reserved. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 1 GPIO0 CS 2 RESET SC18IS600IPW 5 MISO MOSI 6 SDA 7 8 SCL 002aab713 Fig 3. SC18IS600 pin configuration for TSSOP16 Fig 5. SC18IS600 pin configuration for HVQFN24 SC18IS600_601_5 Product data sheet 16 IO5 GPIO0 15 WAKEUP/IO4 14 INT RESET 13 GPIO3 12 V MISO ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin TSSOP16 SC18IS600 SC18IS601 SC18IS600 GPIO0 RESET MISO 5 5 MOSI 6 6 SDA 7 7 SCL 8 8 GPIO1 9 9 GPIO2 10 10 SCLK GPIO3 13 - CLKIN - 13 INT 14 14 WAKEUP/IO4 15 15 IO5 [1] HVQFN24 package die supply ground is connected to both V ground for proper device operation ...
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... NXP Semiconductors 6. Functional description The SC18IS600/601 acts as a bridge between a SPI interface and an I SPI master device to communicate with I Mode 3 of the SPI specification and can operate Mbit/s (SC18IS601). 6.1 Internal registers The SC18IS600/601 provides internal registers for monitoring and control. These registers are shown in paragraphs ...
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... NXP Semiconductors 6.2.1.1 Quasi-bidirectional output configuration Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the pin. This is possible because when the pin outputs a logic HIGH weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW driven strongly and able to sink a large current ...
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... NXP Semiconductors 6.2.1.2 Open-drain output configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the pin when the pin latch contains a logic used as a logic output, a pin configured in this manner must have an external pull-up, typically a resistor tied to V ...
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... NXP Semiconductors Fig 9. 6.2.2 I/O pins state register (IOState) When read, this register returns the actual state of all programmable and quasi-bidirectional I/O pins. When written, each register bit will be transferred to the corresponding I/O pin programmed as output. Table 5. Bit 7 6.2.3 I C-bus address register (I2CAdr) The contents of the register represents the device’ ...
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... NXP Semiconductors 2 The I C-bus clock frequency for the SC18IS601 can be determined using 2 I C-bus clock frequency Table 6. I2CClk (decimal) 5 (minimum 255 (maximum) 2 6.2.5 I C-bus time-out register (I2CTO) The time-out register is used to determine the maximum time that the I allowed to complete a transfer before setting an I Table 7 ...
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... NXP Semiconductors 2 6.2.6 I C-bus status register (I2CStat) This register reports the results of I SC18IS600/601 and Table 8. I C-bus status Register Bit 7 Bit 6 Bit 5 value 0xF0 0xF1 0xF2 0xF3 0xF8 0xF9 SC18IS600_601_5 Product data sheet 2 C-bus transmit and receive transaction between 2 C-bus slave device. ...
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... NXP Semiconductors 6.3 External clock input (SC18IS601) In this device, the processor clock is derived from an external source driving the CLKIN pin. The clock rate may be from MHz. 2 6.4 I C-bus serial interface 2 I C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features: • ...
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... NXP Semiconductors Fig 12. SPI single master multiple slaves configuration 6.6 SPI message format 6.6.1 Write N bytes to I SPI host sends 0x00 NUMBER SLAVE ADDRESS COMMAND OF BYTES CS SCLK MOSI command 0x00 2 Fig 13. Write N bytes to I C-bus slave device The SPI host issues the write command by sending a 0x00 command followed by the total ...
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... NXP Semiconductors 6.6.2 Read N bytes from I Fig 14. Read N bytes from I Once the host issues this command, the SC18IS600/601 will start an I transaction on the I SC18IS600/601 will place this data in the receiver buffer, and will generate an interrupt on the INT pin. The ‘transaction completed’ status can be read in the I2CStat. Note that the data is not returned until a Read Buffer command is performed (see buffer” ...
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... NXP Semiconductors When the host issues a Read Buffer command, the SC18IS600/601 will return the data in the Read Buffer on the MISO pin. Note that the Read Buffer will be overwritten if an additional ‘Read N bytes’ ‘Read after write’ command is executed before the Read Buffer command ...
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... NXP Semiconductors 6.6.7 Write to SC18IS600/601 internal registers Fig 19. Write to SC18IS600/601 internal registers A Write Register function is initiated by sending a 0x20 command followed by an internal register address to be written (see address. Only one register can be accessed in a single transaction. There is no auto-incrementing of the register address. ...
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... NXP Semiconductors 6.6.9 Power-down mode Fig 21. Power-down mode The SC18IS600/601 can be placed in a low-power mode where the internal oscillator is stopped and it will no longer respond to SPI messages. Enter the Power-down mode by sending the power-down command (0x30) followed by the two defined bytes, which are 0x5A followed by 0xA5 ...
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... NXP Semiconductors 8. Static characteristics Table 11. Static characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) I total Power-down mode supply DD(tpd) current V HIGH-LOW threshold voltage th(HL) V LOW-HIGH threshold voltage th(LH) V hysteresis voltage ...
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... NXP Semiconductors 9. Dynamic characteristics Table 12. Dynamic characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter f internal RC oscillator osc(RC) frequency External clock input (SC18IS601); see f oscillator frequency osc T clock cycle time CLCL t clock HIGH time CHCX t clock LOW time CLCX ...
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... NXP Semiconductors Table 13. Dynamic characteristics +85 C (industrial); unless otherwise specified. DD amb Symbol Parameter f internal RC oscillator osc(RC) frequency External clock input (SC18IS601); see f oscillator frequency osc T clock cycle time CLCL t clock HIGH time CHCX t clock LOW time CLCX t clock rise time ...
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... NXP Semiconductors CS SCLK (input) MISO (output) not defined MOSI (input) Fig 22. SPI slave timing (Mode 0.45 V Fig 23. External clock timing SC18IS600_601_5 Product data sheet t SPIF T CLCL t SPILEAD t t SPIF SPIR t t SCLKL SCLKH t t SPIOH SPIOH t t SPIDV SPIDV t SPIA ...
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... NXP Semiconductors Table 14. Additional SPI AC characteristics Symbol Parameter t SPICLK HIGH time SPICLKW t CS HIGH time CSW t SPI enable lag time 1 SPILAG1 t delay time d SCLK t SPILEAD CS SDA 2 Fig 24. SPI to I C-bus timing diagram 8 t CSW ( 1.843 3.687 7.373 Fig 25 function of CLKIN frequency CSW Fig 27 ...
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... NXP Semiconductors 10. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 0.85 mm terminal 1 index area terminal 1 24 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors 11. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 11.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 11.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 12. Abbreviations Table 17. Acronym ASCII CPU GPIO I C-bus LSB MSB PCB SPI UART SC18IS600_601_5 Product data sheet ...
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... NXP Semiconductors 13. Revision history Table 18. Revision history Document ID Release date SC18IS600_601_5 20080728 • Modifications: Table 9 “SPI – SPI configuration for LSB first data order changed from “0x42” to “0x81” – SPI configuration for MSB first data order changed from “0x81” to “0x42” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Internal registers 6.2 Register descriptions . . . . . . . . . . . . . . . . . . . . 6 6.2.1 Programmable IO port configuration register (IOConfi 6.2.1.1 Quasi-bidirectional output configuration . . . . . . 7 6.2.1.2 Open-drain output confi ...