PEB2075N-V13TR Infineon Technologies, PEB2075N-V13TR Datasheet
PEB2075N-V13TR
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PEB2075N-V13TR
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PEB2075N-V13TR Summary of contents
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ICs for Communications ISDN D-Channel Exchange Controller ® (IDEC ) PEB 2075 User´s Manual 05.92 ...
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PEB 2075 Revision History: 05.92 Page Subjects (changes since last revision) Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured ...
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Table of Contents 1 Features ...
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ISDN D-Channel Exchange Controller ® (IDEC ) 1 Features Four independent HDLC channels 64-byte FIFO storage per channel and direction Handling of basic HDLC functions flag detection/generation zero deletion/insertion CRC checking/generation check for abort Address recognition C/I channel handler Single ...
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Pin Configuration (top view RD/DS 7 WR/R DCL 11 IDEC IDEC A1 12 PEB PEB 2075 A0 13 FSC 14 RES 15 ALE ...
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Pin Definitions and Functions Pin Definitions and Functions Pin No. Pin No. Symbol P-LCC-44 P-DIP- AD0 3 2 AD1 1 1 AD2 44 28 AD3 42 27 AD4 41 26 AD5 39 25 AD6 38 24 AD7 ...
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Pin Definitions and Functions (cont’d) Pin No. Pin No. Symbol P-LCC-44 P-DIP- ALE 19 12 INT 15 9 RES 29 18 SD0R 25 16 SD1R 31 20 SD2R 34 22 SD3R 26 17 SD0X 24 15 SD1X 30 ...
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Logic Symbol Semiconductor Group Collision Data Timing Receive DCL FSC CDR R IDEC PEB 2075 ... ... 6) (DS) (R/W) CS ALE C C System 8 Features Tristate Control ...
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CDR SD0X DCL FSC Timing TSC Switching Collision Control HDLC Receiver Transmitter RFIFO XFIFO INT Block Diagram Semiconductor Group SD0R SD1X SD1R Serial Interface Logic Timing Switching Collision Control HDLC Receiver Transmitter RFIFO XFIFO Microcontroller Interface 8 AD0-AD7 RD WR ...
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System Integration Communication Multiplexers The four independent serial HDLC communication channels implemented in the IDEC make the circuit suitable for use in communication multiplexers. The collision detection/resolution capability of the circuit allows statistical multiplexing of packets in one or ...
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PCM Highway Line Transmit TS Receive TS Cards R IDEC PCM Highway Line Transmit TS Receive TS Collision Detect TS Cards R IDEC Figure 1 ® Use of IDEC in Central Signaling / Data Packet Handlers Semiconductor Group PCM Highway ...
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Line Cards in De-Centralized or Mixed Signaling / Data Packet Handling Architectures The IDEC can be used on peripheral line cards to process D-channel packets for ISDN subscribers. The PCM Controller PEB 2055 has the layer-1 controlling capacity and a ...
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Line Transceivers S/U IOM X8 D S/U R IDEC Legend: c.c.s/p = Common channel for signaling and for packed data, C/I, MON = Control/Indication and MONITOR channels for the Figure 2 Line Card in a De-Centralized D-Channel Handling Architecture Semiconductor ...
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R IOM Line Transceivers D b) IOM Line Transceivers D IDEC Packets will be discarded by the receiver Legend Time-Slot for p packets s = Time-Slot for s packets Coll s-p = Time-Slot containing ...
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Functional Description 2.1 General Functions and Device Architecture The IDEC is an HDLC controller which handles four HDLC communication channels, each channel fully independent and programmable by its own register set. The circuit performs the following functions: – Extraction ...
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In the quad connection configuration two modes are distinguished as follows: – Each connection is a time slotted highway, the lengths and positions of the time slots are programmable (quad connection time slot mode); – Each connection is a communication ...
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Quad Connection TS Mode Receive Transmit Receive Transmit Receive Transmit Receive Transmit Collision Data b) Quad Connection Common Control Mode Strobe Receive Transmit Receive Transmit Receive Transmit Receive Transmit Collision Data Figure 5a, 5b Operating Modes of the IDEC ...
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Single Connection TS Mode Receive Transmit Collision Data d) Single Connection IOM Receive Transmit Collision Data Figure 5c, 5c Operating Modes of the IDEC Semiconductor Group Programmable Time-Slots Slave/Multi-Master Collision Mode ® Mode R IOM A ...
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Single Connection TS Mode Programmable Time-Slots B C Receive Transmit ® f) Single Connection IOM IOM Receive Transmit Figure 5e, 5f Operating Modes of the IDEC Semiconductor Group Master Collision Mode Mode A ...
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Interfaces Microcontroller Interface The IDEC is programmable over an 8-bit parallel microcontroller interface. Easy and fast microprocessor access is provided by 8-bit address decoding on chip. The interface consists of 13 (19) lines and is directly compatible with processors ...
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Table 2 (cont’d) Microcontroller Interface Signals of the IDEC Symbol Input (I) Output (O) Open Drain (OD) ALE I INT OD RES I In addition to 8-bit processors, the IDEC supports a direct connection to 16-bit processors. Thus, through an ...
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Individual Functions 2.4.1 Channel Access The four HDLC controllers of the IDEC are connected to the serial interfaces as shown in table 3. The table indicates the selection of the data channel, the selectable time slot widths, the output ...
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Table 3 HDLC Controller Channel Selection and Characteristics Mode Channel MDS1 MDS0 SD0R SD0R SD0R SD0R SD0X SD0X SD0X SD0X Single 0 1 SD0R SD1R SD2R SD3R SD0X SD1X SD2X SD3X Quad connection 1 0 SD0R ...
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The tristate control output line TSC marks the time slot when data is transmitted/received by the HDLC controller B. The position of a time slot with respect to FSC function of the TSR register contents, is shown in ...
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Quad Connection Common Control Mode Channel selection is performed by an active high strobe signal provided through the FSC input. The strobe signal is common to all four HDLC channels. The TSC output is active when the FSC strobe is ...
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Multiplexed Frame Structure of the IOM FSC DCL R CH0 CH1 Data IN IOM R Data OUT IOM CH0 CH1 B1 Byte 1 b) Assignment of HDLC Channels in IOM R IOM CH0 VIS = 0 HDLC Channels VIS ...
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HDLC Communication Functions Basic HDLC Functions Each one of the four controller channels handles the following basic HDLC functions. Receive direction – Flag detection A zero followed by six consecutive ones and another zero is recognized as a flag. ...
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Reception and Transmission Functions FIFO Structure Each HDLC controller uses a 64-byte FIFO per direction for the intermediate storage of data packets. All data bytes between the opening flag and the CRC field of an HDLC frame are passed through ...
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Reception of Frames Address Compare Before a receive frame is stored, its address (the first byte following the opening flag) may optionally be compared against three fixed values. SAPG "Group SAPI" SAPS "Signaling SAPI" SAPP "Packet SAPI" Each address compare ...
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Frame Storage When a frame is accepted stored in the receive FIFO. In the case of a frame of length less than to 64 bytes, the whole frame may be stored in the receive FIFO. After the first ...
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Bytes Inaccessible Bytes Accessible to C Figure 10 Receive FIFO in the Case of Short Frames The interrupts accumulating in the process are incorporated into a queue and transferred one by one to the microcontroller as ...
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Transmission of Frames bytes of intermediate storage are provided per HDLC controller in the transmit direction. After bytes have been written to the FIFO, transmission is started by a software command (XHF). If the ...
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Collision Control and Switching Functions The IDEC possesses flexible collision control capabilities which are totally transparent to the microcontroller. The collision control modes enable use of the circuit in statistical multiplexing applications or in centralized or de-centralized packet switches. ...
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Unconditional Transmission Mode The HDLC controller transmits frames without collision detection on the transmit line (time channel). Slave Mode The input CDR (Collision Data Receive) is used to control transmission of frames. This input is common to all HDLC controllers ...
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The slave mode is applicable in all of the basic operation modes, in both single connection and quad connection applications. However, there is only one CDR line. This should especially be noted if: – the IDEC is configured in the ...
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DCL or DCL ÷ 2 Single Connection Mode: SDOX Quad Connection Mode: SDiX ... 3 CDR Figure 13 Collision Detection in the Multi-Master Mode (example) An automatic priority adjustment is implemented in the multimaster mode. Thus, when ...
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TS Mode Programmable Time-Slots (TSR) R IOM Mode Fixed Time-Slots SD0X SD0R Figure Connections in the Master Mode Semiconductor Group Functional Description Controller A Collision Control HDLC Controller Controller B Programmable Time-Slots (TSR) Controller C Controller ...
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In the TS mode the time slot programmed via the Time-Slot Select Register TSR applies simultaneously to SD0X/SD0R and to the auxiliary lines CDR, SD1X and SD2X. In the IOM mode the TSR register selects a time channel on the ...
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Collision Resolution in the Master Mode with Programmable Priority (FHF) Figure 15 Semiconductor Group Functional Description 39 ITD02722 ...
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Note on Data Delay in Master Mode The data bits are switched from SD0R to SD1X and from CDR to SD0X with a minimum delay as shown in figure 16. Two different cases are distinguished mode. In this ...
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Bit delay for coinciding channel/time slot position on SD0R/SD0X and on CDR/SD1X. Figure 16a Bit Delay from SD0R/CDR to SD1X/SD0X Bit delay for non-identical channel/time slot position on SD0R/SD0X and on CDR/SD1X (possible only when SD0R/SD0X is an IOM interface). ...
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Test Functions A test loop is provided in each of the four HDLC controllers of the IDEC. When the test loop is activated, the input and the output of the HDLC channel are connected together. The test loop control ...
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Operational Description 3.1 Microprocessor Interface Operation The IDEC microcontroller interface can be selected to be either of the 1. Motorola type with control signals CS, R/W, DS; address bus A0 … 6; data bus AD0 … Siemens/lntel ...
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Table 7 State of IDEC After a Hardware Reset Register Name Value after Hardware Reset (hex) Common registers ACR 00 CCR 00 VISR 00 VISM 00 Individual registers ISTA 00 ISM 00 STAR 50 ...
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Initialization The purpose of the initialization is to set the IDEC into a state where it is able to correctly transfer HDLC frames and to manage collisions according to the requirements of the application. The initialization process is divided ...
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Secondly, each of the HDLC channels is initialized via its own register set as shown in table 9. The optional address comparison mode for each HDLC channel is selected by programming the ACR register, located in the common address space ...
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Mask ISM.ISTA Int. Status A Figure 17 Interrupt Structure of the IDEC A read of the ISTA clears the register and deactivates the INT line. The position which the four bits of the Vectored Interrupt Status Register occupy on the ...
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Processing After being initialized via the configuration/mode registers listed in tables 8 and 9 the IDEC is operational. The control of the data transfer is performed by commands from the microcontroller written in the Command Register (CMDR). Events pertaining ...
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R IDEC HDLC Receiver Figure 18 Reception of an HDLC Frame Transmit Frame Processing After checking the XFIFO status by polling the Transmit FIFO Write Enable (XFW) bit or after a Transmit Pool Ready (XPR) interrupt ...
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R IDEC HDLC Transmitter Data Transfer Figure 19 Transmission of an HDLC Frame The microcontroller does not necessarily have to transfer a frame in blocks of 32 bytes matter of fact, the sub-blocks issued by the microcontroller ...
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Table 10 Possible Interrupt Causes and Reactions Mnemonic Meaning RPF Receive Pool Full RME Receive Message End RFO Receive Frame Overflow XPR Transmit Pool Ready XDU Transmit Data Underrun Semiconductor Group Operational Description Reaction Read 32 bytes from RFIFO and ...
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Table 11 lists the most important commands which are issued by a microcontroller by setting one or several bits in the Command Register (CMDR). Table 11 List of Commands Command Hex Bit 7 … 0 Mnemonic RMC 80 1000 RRES ...
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Detailed Register Description The following symbols are used throughout chapter 4 x... don’t care n... not used. It has to be set to logical "0" in write accesses but may be switched by the IDEC to either logical level ...
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Figure 20 IDEC Register Map for a Multiplexed Address Bus Semiconductor Group Read Write F ACR ACR CCR CCR VISR VISM 54 ...
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The address map of the individual registers of each channel is shown in table 12. In order to obtain the actual address of a register, a "base" has to be added to the address given in the table, as follows: ...
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Non-Multiplexed Address Bus The address layout is shown in figure 21. The address map of the individual registers of each channel is shown in table 13. In order to obtain the actual address of a register, a "base" has to ...
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Figure 21 IDEC Register Map for Non-Multiplexed Address Bus Semiconductor Group Read Write ACR ACR VISR VISM CCR CCR 57 Register Description Channel-A Register Locations Channel-B Register Locations ...
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Register Description Common Registers Common Configuration Register (CCR) Value after reset: 000n0000B 7 MDS1 MDS0 VIS MDS1,0 Mode Select MDS1 MDS0 VIS Vectored Interrupt Selection 0 IOM channel ...
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The ODS bit selects the driver type simultaneously on all data outputs (and control output SD2X in master mode). However, in the single connection IOM mode SD0X is open-drain independent of the value of ODS. Address Compare Register (ACR) Value ...
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The HDLC address compare logic is summarized in the table below. SCM SCG SCS ...
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Vectored Interrupt Status Register (VISR) Value after reset: xxxx0000B IC3 IC2 IC1 IC0-3 Interrupt from Channel A-D When VISR is read, these four bits are placed on the P data bus with an offset ...
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Individual Channel Registers FlFOs RFIFO (read), XFIFO (write) The FlFO’s have an identical address range. All the 32 addresses give access to the ‘current’ FIFO location. Note on RFIFO The RFBC register bits indicate the number of ...
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Status / Command Registers Interrupt Status Register (ISTA) Value after reset RME RPF RFO RME Receive Message End. One complete frame of length less than 32 bytes, or the last part of a frame at least 32 ...
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Status Register (STAR) Value after reset XDOV XFW BSY XDOV Transmit Data Overflow. More than 32 bytes have been written into the XFIFO. XFW Transmit FIFO Write Enable. Data can be entered into the XFIFO. BSY Busy ...
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Command Register (CMDR) Value after reset RMC RRES RMD RMC Receive Message Complete. Reaction to RPF or RME internupt. The receive FIFO pool currently accessible by the microcontroller is released for a subsequent frame (or 32-byte block ...
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Mode Register (MODE) Value after reset TLP CMS1 CMS0 TLP Test Loop Input and output of HDLC channel are connected together when TLP = 1. The test loop is either transparent (if MDS1,0 = 01, 10) or ...
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Command/lndicate Channel Receive Channel (CIR0 - 3) (read) Address: 23,2A + offset (multiplexed offset (demux) Reset value: nnnn1111 B bit bit7: Not used. bit6: Not used. bit5: Not used. bit4: Not ...
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Recelve Frame Byte Counter (RFBC) Value after reset RDC7 RDC6 RDC5 RDC7-0 Receive Data Count Total number of bytes of received frame, including the status byte. The contents of the register are valid after an RME interrupt. ...
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Electrical Characteristics Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on any pin with respect to ground DC Characteristics ± Parameter L-input ...
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AC Characteristics ± Inputs are driven to 2.4 V for a logical "1" and to 0.4 V for a logical "0". Timing measurements are made at ...
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Microcontroller Interface TimingmP Read Cycle Siemens/Intel Bus ModemP Read CyclemP Read CyclemP Read Cycle P Read Cycle AD0 - AD7 Figure 23 P Write Cycle AD0 -AD7 Figure 24 Multiplexed Address Timing ALE WR ...
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Non - Multiplexed Address Timing Figure 26 Motorola Bus Mode P Read Cycle R Figure 27 Semiconductor Group t AS Address t DSD t ...
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P Write Cycle R AD0 - AD7 Figure 28 Address Timing AD0 - AD5 Figure 29 Semiconductor Group t DSD t RWD Data ...
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Interface Timing Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time Address hold time ALE guard time RD Delay after WR setup RD pulse width ...
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Serial Interface Timing DCL Characteristics 2.0 V 0.8 V Figure 30 Definition of DCL Period and Width Parameter DCL period DCL high DCL low Semiconductor Group Symbol Limit Values min. typ. t 230 P 160 t ...
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Input/Output Characteristics FSC in Single Connection Modes and Quad Connection in TS Mode DCL FSC t FS Data OUT DCL Rate equal to Data Rate Data IN Data OUT DCL Rate equal to twice the Data Rate Data IN Figure ...
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FSC Timing Characteristics Parameter FSC set-up time FSC setup time* FSC hold time Output data delay from DCL Input data set-up Input data hold Output data delay from FSC* *Note: This delay is applicable in two cases when the first ...
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FSC in Quad Connection Common Control Mode DCL t FH1 FSC High Impedance Data OUT Data IN Figure 32 FSC Characteristics (strobe) Parameter FSC set-up time FSC hold time Output data from high impedance to active Output data from active ...
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DCL Data OUT Data IN TSC Figure 33 Data I/O Characteristics Parameter Output data delay from DCL Input data set-up Input data hold TSC delay from DCL Data OUT: SD0X in single connection modes SD0X, SD1X, SD2X, SD3X in quad ...
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Appendix 1. The version number (STAR0-3:VN1, VN0) has been incremented to 10 bin. 2. IDEC version A3 has a C/I channel handler implemented. If CCR:bit3 is set to “0” in all write accesses as specified in the IDEC Technical ...
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Package Outlines Plastic Dual-in-Line Package, P-DIP-28 2. Index Marking Plastic-Leaded Chip Carrier, P-LCC-44 (SMD) SMD = Surface Mounted Device Semiconductor Group +0.1 0.45 1.5 1.5 max 15 14 0.25 35.9 -0.4 81 Package Outlines 15.24 ±0.2 +0.1 ...