TDA8034HN/C1,157 NXP Semiconductors, TDA8034HN/C1,157 Datasheet - Page 7

• Manufacturer Part Number: TDA8034HN/C1,157
• Description: IC SMARD CARD INTERFACE 24HVQFN
• Manufacturer: NXP Semiconductors

Specifications of TDA8034HN/C1,157

• Controller Type: Smart Card Interface
• Interface: Analog
• Voltage - Supply: 1.8V, 3V, 5V
• Current - Supply: 65mA
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
TDA8034HN
Product data sheet
8.3 Clock circuits
The clock signal from pin CLK to the card is either supplied by an external clock signal
connected to pin XTAL1 or generated using a crystal connected between pins XTAL1 and
XTAL2. The TDA8034HN automatically detects if an external clock is connected to
XTAL1, eliminating the need for a separate pin to select the clock source.
Automatic clock source detection is performed on each activation command (falling edge
of the signal on pin CMDVCCN). The presence of an external clock on pin XTAL1 is
checked during a time window defined by the internal oscillator. If a clock is detected, the
internal crystal oscillator is stopped. If a clock is not detected, the internal crystal oscillator
is started. When an external clock is used, it is mandatory that the clock is applied to pin
XTAL1 before the falling edge of the signal on pin CMDVCCN.
The clock frequency is selected using pins CLKDIV1 and CLKDIV1 to be either f
1
Remark: The levels on both pins must not be allowed to change simultaneously but
should be separated by a minimum of 10 ns.
The frequency change is synchronous and as such during transition, no pulse is shorter
than 45 % of the smallest period. In addition, only the first and last clock pulse around the
change has the correct width. When dynamically changing the frequency, the modification
is only effective after 10 clock periods on pin XTAL1.
The duty cycle of f
is connected to pin XTAL1, its duty cycle must be between 48 % and 52 %.
When the frequency of the clock signal on pin CLK is either f
1
Table 4.
Pin CLKDIV1 level
LOW
LOW
HIGH
HIGH
∨
∨
Fig 5.
2
8
f
f
xtal
xtal
, the frequency dividers guarantee a duty cycle between 45 % and 55 %.
or
enclkin and clkxtal are internal signal names.
Basic layout for using an external clock
1
Clock configuration
∨
4
f
xtal
All information provided in this document is subject to legal disclaimers.
or
xtal
1
Rev. 3.0. — 17 January 2011
on pin CLK should be between 45 % and 55 %. If an external clock
∨
8
f
xtal
as shown in
Pin CLKDIV2 level
LOW
HIGH
HIGH
LOW
enclkin
DIGITAL
XTAL1
Table
MULTIPLEXER
clkxtal
CRYSTAL
4.
XTAL2
001aak992
Pin CLK frequency
1
1
1
f
xtal
xtal
∨
∨
∨
8
4
2
,
f
f
f
TDA8034HN
xtal
xtal
xtal
1
∨
2
Smart card interface
f
xtal
© NXP B.V. 2011. All rights reserved.
,
1
∨
4
f
xtal
xtal
or
,
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