DP83815DVNG/NOPB National Semiconductor, DP83815DVNG/NOPB Datasheet - Page 49

• Manufacturer Part Number: DP83815DVNG/NOPB
• Description: IC CTLR/LAYER INT PCI 144-LQFP
• Manufacturer: National Semiconductor

Specifications of DP83815DVNG/NOPB

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: PCI
• Voltage - Supply: 3.3V
• Current - Supply: 170mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83815DVNG; *DP83815DVNG/NOPB; DP83815DVNG

4.0 Register Set
4.2.8 Interrupt Enable Register
The Interrupt Enable Register controls the hardware INTR signal.
4.2.9 Transmit Descriptor Pointer Register
This register points to the current Transmit Descriptor.
31-1
31-2
Bit
Bit
1-0
0
Bit Name
Bit Name
TXDP
IE
Offset: 0018h
Offset: 0020h
(Continued)
Tag: IER
Tag: TXDP
unused
Interrupt Enable
When set to 1, the hardware INTR signal is enabled. When set to 0, the hardware INTR signal will be
masked, and no interrupts will be generated. The setting of this bit has no effect on the ISR or IMR. This
provides the ability to disable the hardware interrupt to the host with a single access (eliminating the
need for a read-modify-write cycle).
Transmit Descriptor Pointer
The current value of the transmit descriptor pointer. When the transmit state machine is idle, software
must set TXDP to the address of a completed transmit descriptor. While the transmit state machine is
active, TXDP will follow the state machine as it advances through a linked list of active descriptors. If the
link field of the current transmit descriptor is NULL (signifying the end of the list), TXDP will not advance,
but will remain on the current descriptor. Any subsequent writes to the TXE bit of the CR register will
cause the transmit state machine to reread the link field of the current descriptor to check for new
descriptors that may have been appended to the end of the list. Transmit descriptors must be aligned on
an even 32-bit boundary in host memory (A1-A0 must be 0).
unused
Access: Read Write
Access: Read Write
Size: 32 bits
Size: 32 bits
49
Description
Description
Hard Reset: 00000000h
Hard Reset: 00000000h
Soft Reset: 00000000h
Soft Reset: 00000000h
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