DP83815DVNG/NOPB National Semiconductor, DP83815DVNG/NOPB Datasheet - Page 60

• Manufacturer Part Number: DP83815DVNG/NOPB
• Description: IC CTLR/LAYER INT PCI 144-LQFP
• Manufacturer: National Semiconductor

Specifications of DP83815DVNG/NOPB

• Controller Type: Ethernet Controller, MAC/BIU
• Interface: PCI
• Voltage - Supply: 3.3V
• Current - Supply: 170mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DP83815DVNG; *DP83815DVNG/NOPB; DP83815DVNG

Subject to change without notice.
4.0 Register Set
4.2.18 Receive Filter Logic
The Receive Filter Logic supports a variety of techniques
for qualifying incoming packets.
options include Accept All Broadcast, Accept All Multicast
and Accept All Unicast packets. These options are enabled
by setting the corresponding bit in the Receive Filter
Control Register, RFCR. Accept on Perfect Match, Accept
on Pattern Match, Accept on Multicast Hash and Accept on
Unicast Hash are more robust in their filtering capabilities,
but require additional programming of the Receive Filter
registers and the internal filter RAM.
Accept on Perfect Match
When enabled, the Perfect Match Register is used to
compare against the DA for packet acceptance. The
Perfect Match Register is a 6-byte register accessed
indirectly through the RFCR. The address of the internal
receive filter register to be accessed is programmed
through bits 8:0 of the RFCR. The Receive Filter Data
Register, RFDR, is used for reading/writing the actual data.
Octet 0 of the Perfect Match Register corresponds to the
first octet of the packet as it appears on the wire. Octet 5
corresponds to the last octet of the DA as it appears on the
wire.
The following steps are required to program the RFCR to
accept packets on a perfect match of the DA.
Example: Destination Address of 08-00-17-07-28-55
RX Filter Address: 000h - Perfect Match octets 1-0
iow l $RFCR (0000)
iow l $RFDR (0008)
iow l $RFCR (0002)
iow l $RFDR (0717)
iow l $RFCR (0004)
iow l $RFDR (5528)
iow l $RFDR
($RFEN|$APM)
002h - Perfect Match octets 3-2
004h - Perfect Match octets 5-4
(Continued)
write address, octets 1-0
write address, octets 3-2
write address, octets 5-4
enable filtering, perfect match
perfect match register, octets 1-0
perfect match register, octets 3-2
perfect match register, octets 5-4
The most basic filtering
60
Accept on Pattern Match
The Receive Filter Logic provides access to 4 separate
internal RAM-based pattern buffers to be used as
additional perfect match address registers. Pattern buffers
0 and 1 are 64 bytes deep, allowing perfect match on the
first 64 bytes of a packet, and pattern buffers 2 and 3 are
128 bytes deep, allowing perfect match on the first 128
bytes of a packet.
When one or more of the Pattern Match enable bits are set
in the RFCR, a packet will be accepted if it matches the
associated pattern buffer. As indicated above, the pattern
buffers are 64 and 128 bytes deep organized as 32 or 64
words, where a word is 18 bits. Bits 17 and 18 of a
respective word are mask bits for byte 0 and byte 1 of the
16-bit data word (bits 15:0). An incoming packet is
compared to each enabled pattern buffer on a byte by byte
basis for a specified count. Masking a pattern byte results
in a byte match regardless of its value (a don’t care). A
count value must be programmed for each pattern buffer to
be used for comparison. The minimum valid count is 2 (2
bytes) and the maximum valid count is 32 for pattern
buffers 0 and 1, and 64 for pattern buffers 2 and 3. The
pattern count registers are internal receive filter registers
accessed through the RFCR and the RFDR The Receive
Filter memory is also accessed through the RFCR and the
RFDR. A memory map of the internal pattern RAM is
shown in Figure 4-1.
Rev O
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