DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 64

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

7.0 RIC2A Registers
Packet Compress Decode Register (Page 0H Address 18H)
This register is used to determine the number of bytes in the data field of a packet which are transferred over the manage-
ment bus when the packet compress option is employed. The register bits perform the function of a direct binary decode.
Thus up to 255 bytes of data may be transferred over the management bus if packet compression is selected.
Global Security Register (GSR) (Page 0H Address 1DH)
This register provides various security configuration options. For example, enable learning mode for all the ports; starting
address comparison; use the modified packet status register 5 for the management bus; generate random pattern on
source address mismatch; disable port on source address mismatch.
D0
D1
D2
D3
D4
D5
D6
D7
Bit
R/W
R/W
R/W
R
R/W
R
R/W
R
R/W
PCD7
resv
D7
D7
SAC
GRP
MPS
resv
DSM
resv
GLME
resv
Symbol
GLME
(Continued)
PCD6
D6
D6
Start Address Comparison
0: Do not begin comparison
1: Begin comparison
Generate Random Pattern: This bit controls generating the random pattern on
a valid source address mismatch. In any event, the Hub Manager will be
informed on the SA mismatch.
0: Generate the random pattern
1: Do not generate the random pattern
Modify Packet Status Register 5: This bit enables modifying the packet status
register 5, PSR5 on the 7 management bytes, over the management bus.
0: Do not modify the PSR5
1: Modify the PSR5
Reserved for Future Use
For proper operation, this bit must be 0.
Disable the Port on a Source Address Mismatch
0: Do not disable the port on a valid source address mismatch
1: Disable the port on a valid source address mismatch
Reserved for Future Use
Global Learn Mode Enable
0: Do not enable the learn mode for all ports
1: Enable the learn mode for all ports
Note: The GLME is not a status bit. Reading this bit indicates what value was
last written to it.
Reserved for Future Use
reads as a logic 0
PCD5
resv
D5
D5
DSM
PCD4
D4
D4
64
PCD3
resv
D3
D3
Description
MPS
PCD2
D2
D2
PCD1
GRP
D1
D1
PCD0
SAC
D0
D0
www.national.com