DP83953VUL National Semiconductor, DP83953VUL Datasheet - Page 8

• Manufacturer Part Number: DP83953VUL
• Description: IC CTRLR RIC REPEATER 160-PQFP
• Manufacturer: National Semiconductor

Specifications of DP83953VUL

• Controller Type: Ethernet Repeater Interface Controller
• Interface: IEEE 802.3
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 870mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-MQFP, 160-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83953VUL

2.0 Pin Descriptions
TT = TTL compatible, B = Bi-directional, C = CMOS compatible, OD = Open Drain, I = Input, O = Output,
Z = high impedance,
Inter-RIC Bus Pins
ACKI
ACKO
IRD
IRE
IRC
COLN
PKEN
CLKIN
ACTND
ACTNS
ANYXND
ANYXNS
Pin Name
Pin No.
100
53
60
76
77
78
75
72
62
52
61
51
(Continued)
Driver
Type
OD
OD
TT
TT
TT
TT
TT
TT
TT
TT
TT
C
B,Z
B,Z
B,Z
B,Z
I/O
O
O
O
O
I
I
I
I
ACKNOWLEDGE INPUT: Input to the network ports' arbitration
chain.
ACKNOWLEDGE OUTPUT: Output from the network ports' arbi-
tration chain.
INTER-RIC DATA: When asserted as an output this signal pro-
vides a serial data stream in NRZ format. The signal is asserted by
a RIC2A when it is receiving data from one of its network seg-
ments. The default condition of this signal is to be an input. In this
state it may be driven by other devices on the Inter-RIC bus.
INTER-RIC ENABLE: When asserted as an output this signal pro-
vides an activity framing enable for the serial data stream. The sig-
nal is asserted by a RIC2A when it is receiving data from one of its
network segments. The default condition of this signal is to be an
input. In this state it may be driven by other devices on the Inter-
RIC bus.
INTER-RIC CLOCK: When asserted as an output this signal pro-
vides a clock signal for the serial data stream. Data (IRD) is
changed on the falling edge of the clock. The signal is asserted by
a RIC2A when it is receiving data from one of its network seg-
ments. The default condition of this signal is to be an input. When
an input, IRD is sampled on the rising edge of the clock. In this
state it may be driven by other devices on the Inter-RIC bus.
COLLISION ON PORT N: This denotes that a collision is occurring
on the port receiving the data packet. The default condition of this
signal is to be an input. In this state it may be driven by other de-
vices on the Inter-RIC bus.
PACKET ENABLE: This output acts as an active high enable for
an external bus transceiver (if required) for the IRE, IRC IRD and
COLN signals. When high the bus transceiver should be transmit-
ting on to the bus, i.e. this RIC2A is driving the IRD, IRE, IRC, and
COLN bus lines. When low the bus transceiver should receive from
the bus.
40 MHz CLOCK INPUT: This input is used to generate the
RIC2A's timing reference for the state machines, and phase lock
loop decoder.
ACTIVITY ON PORT N DRIVE: This output is active when the
RIC2A is receiving data or collision information from one of its net-
work segments.
ACTIVITY ON PORT N SENSE: This input senses when this or an-
other RIC2A in a multi-RIC2A system is receiving data or collision
information.
ACTIVITY ON ANY PORT EXCLUDING PORT N DRIVE: This
output is active when a RIC2A is experiencing a transmit collision
or multiple ports have active collisions on their network segments.
ACTIVITY ON ANY PORT EXCLUDING PORT N SENSE: This in-
put senses when this RIC2A or other RIC2As in a multi-RIC2A sys-
tem are experiencing transmit collisions or multiple ports have
active collisions on their network segments.
8
Description
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