DP83953VUL National Semiconductor, DP83953VUL Datasheet
DP83953VUL
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DP83953VUL Summary of contents
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... TRI-STATE are registered trademarks of National Semiconductor Corporation. ™ 100RIC is a trademark of National Semiconductor Corporation ™ SONIC is a trademark of National Semiconductor Corporation Ethernet is a trademark of Xerox Corporation ® GAL is a registered trademark of Lattice Semiconductor ® PAL is a registered trademark of and license from Advanced Micro Devices, Inc. ...
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General Description (continued) The RIC2A repeater consists of two major functional blocks: The segment specific block and the shared func- tional blocks. The segment specific block incorporates rele- vant IEEE specifications on a per port basis. The shared functional blocks ...
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... Connection Diagram Order Number DP83953VUL NS Package Number VUL160A 3 www.national.com ...
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Connection Diagram (Continued) PIN NAME PIN NO. PIN NAME GNDP13 TXO13- 39 GND TXO13+ 38 IRC TXO12- 37 IRE TXO12+ 36 IRD GNDP12 35 COLN V P12 RXI12- 33 GND RXI12+ 32 ...
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Pin Descriptions Driver Pin Name Pin No. Type Network Interface Pins RXI2- to RXI13- TP RXI2+ to RXI13+ TP TXO2- to TXO13- TP TXO2+ to TXO13+ TP FILTTL 153 TT REQ 4 Analog RTX 5 Analog AUI Port CD1+ ...
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Pin Descriptions (Continued) Pin Name Pin No. Processor Bus Pins RA0 - RA4 STR0 63 STR1 BUFEN 70 RDY 69 ELI 68 Driver I/O Type TT I REGISTER ADDRESS INPUTS: These five pins are used ...
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Pin Descriptions (Continued) RTI 67 CDEC MLOAD TTL compatible Bi-directional CMOS compatible Open Drain Input Output high impedance C ...
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Pin Descriptions (Continued) Driver Pin Name Pin No. Type Inter-RIC Bus Pins ACKI 53 TT ACKO 60 TT IRD 76 TT IRE 77 TT IRC 78 TT COLN 75 TT PKEN 72 C CLKIN 100 TT ACTND 62 OD ...
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Pin Descriptions (Continued) Pin Name Pin No. Management Bus Pins MRXC 59 MCRS 56 MRXD 57 MEN 58 PCOMP 50 External Decoder Pins RXMPLL 71 Test Pins TEST_(12:7) 154-159 TEST_(6:2) 44-48 TEST_1 2 Power and Ground Pins V 1, ...
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Block Diagrams Figure 1. Shared Repeater and Segment Functional Blocks 10 www.national.com ...
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Block Diagrams (Continued) Figure 2. RIC2A Port Architecture Security Block Diagram Note: The block diagram for the RIC2A, when used in the non-secure mode, is identical to the “shared” repeater functional block diagram.( Figure 1 ). But, in secure ...
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Functional Description The IEEE 802.3 repeater specification delineates the func- tional criteria that all compliant repeater systems must adhere to. An implementation of these requirements strongly suggest a multiport modular design style. In such a design, functionality is split ...
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Functional Description the case of a source address mismatch, the RIC2A will immediately switch to a random bit pattern on both the local transmitting ports and the IRB. The main state machine operates in conjunction with a series of ...
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Functional Description The notification of collisions occurring across the network is just as important as data transfers. The Inter-RIC bus has a set of status lines capable of conveying collision information between RIC2As in order to ensure that their ...
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Functional Description Repeater Port and Main State Machines The Port and Main State Machines are described with ter- minology used in the IEEE Repeater specification. For a detailed explanation of terms, please refer to that specifica- tion. References made ...
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Functional Description Figure 4. IEEE Repeater Main State Diagram (Continued) 16 www.national.com ...
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Functional Description The Port State Machine (PSM) The two primary functions of the PSM are to: 1. Control the transmission of repeated data, pseudo ran- dom data, and jam signals over the attached segments. 2. Determine if a port ...
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Functional Description The IRB connects multiple RIC2As to realize the following operations: Port N Identification (which port the repeater receives data from) Port M Identification (which port last experienced a colli- sion) Data Transfer RECEIVE COLLISION identification Inter-RIC Function ...
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Functional Description Methods of RIC2A Cascading In order to build multi-RIC2A repeaters, PORT N and PORT M identification must be performed across all the RIC2As in the system. Inside each RIC2A, the PSMs are arranged in a logical arbitration ...
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Functional Description Figure 5 shows two RIC2As A and B, daisy chained together with RIC2A-A positioned at the top of the chain packet is received at port B1 of RIC2A-B, and then repeated to the other ports ...
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Functional Description Note: 1* The activity shown represents the transmitted signal after being looped back by the attached transceiver. (Continued) Figure 6. Data Repetition 21 www.national.com ...
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Functional Description Note: 1 SEND PREAMBLE, SEND SFD, SEND DATA AUI port shown. (Continued) Figure 7. Receive Collision 22 www.national.com ...
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Functional Description Receive Collisions (AUI Port only) A receive collision is a collision which occurs on the net- work segment attached to the AUI port. The collision is "received" similar manner as a data packet is received, ...
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Functional Description on its segment, but in addition it is higher in the arbitration chain. This priority yields no benefits for port A1 since the ANYXN signal is still active. There are now two sources driving ANYXN, the MSMs ...
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Functional Description Note: The Inter-RIC bus is configured to use active low signals. AUI port shown (Continued) Figure 8. Transmit Collision 25 www.national.com ...
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Functional Description Note: 1* The IEEE Specification does not have a jabber protect state defined in its main state diagram, this behavior is defined in an additional MAU Jabber Lockup Protection state diagram. Note: The Inter-RIC bus is configured ...
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Functional Description Note Bus Drive Enable active high, /RE = Bus Receive Enable active low Note: The Inter-RIC bus is configured to use active low signals. Figure 10. External Bus Transceiver Connection Diagram 4.5 Description Of Hardware ...
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Functional Description Some bus transceivers are of the inverting type. To allow the Inter-RIC bus to utilize these transceivers, the RIC2A may be configured to invert the active states of the ACTN, ANYXN, COLN and IRE signals from active ...
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Functional Description Table 1. Pin Definitions for Options in the Mode Load Operation Program- Pin Effect when ming Name Bit is 0 Function D0 SCRTY Security Mode D1 TW2 5 bits D2 CCLIM 63 D3 LPPART Selected D4 OWCE ...
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Functional Description 4.7 Description Of Hardware Connection For Pro- cessor And Display Interface Display Update Cycles The RIC2A possesses control logic and interface pins which may be used to provide status information concern- ing activity on the attached network ...
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Functional Description Table 3. Status Display Pin Functions in Maximum Mode Signal Pin Name D0 Provides status information concerning the Link Integrity status of 10BASE-T segments. This signal should be connected to the data inputs of the chosen pair ...
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Functional Description Figure 12. Maximum Mode LED Display (All Available Status Bits Used) (Continued) 32 www.national.com ...
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Functional Description (Continued) Figure 13. Processor Connection Diagram 33 www.national.com ...
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Functional Description Processor Access Cycles Access to the RIC2A's on-chip registers is made via its pro- cessor interface, which utilizes conventional non-multi- plexed address (five bit) and data (eight bit) busses. Also, the data bus provides data and address ...
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HUB MANAGEMENT SUPPORT The RIC2A provides information regarding the status of its ports and the packets being repeated. This data is avail- able in three forms: 1. Counted Events - Network events accumulated into the RIC2A's 16 bit Event ...
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HUB MANAGEMENT SUPPORT The port event counters may also be controlled by the Counter Decrement (CDEC) pin. As the name suggests, a logic low state on this pin will decrement all the counters by a single value. The pulses ...
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HUB MANAGEMENT SUPPORT Short Event reception (SE): This flag goes active if the received packet is less than 74 bits long and no collision occurs during reception. 5.3 Management Interface Operation The Hub Management interface provides a mechanism to ...
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HUB MANAGEMENT SUPPORT Thus all of the other status fields can be correctly attrib- uted to the relevant port. 2. The status flags that the RIC2A produces for the event counters or recording latches are supplied with each packet ...
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HUB MANAGEMENT SUPPORT Packet status Register PSR PSR(0) PSR(1) PSR(2) PSR(3) Collision Bit Timer PSR(4) Lower Repeat Byte Count Note 2 PSR(5) MPS=0 Upper Repeat Byte Count ---------- MPS=1 PSR(6) Inter Frame Gap Bit Timer Note 1: These registers ...
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HUB MANAGEMENT SUPPORT Figure 15. (Continued) Operation of the Management Bus 40 www.national.com ...
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HUB MANAGEMENT SUPPORT Packet Status Register Bit Symbol D0 resv Reserved for future use: This bit is currently undefined. Management software should not examine the state of this bit. D1 PCOMPD Packet Compression Done: ...
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HUB MANAGEMENT SUPPORT Packet Status Register OWC Bit Symbol D(1:0) CT(9:8) Collision Timer Bits 9 and 8: These two bits are the upper bits of the collision bit timer. D2 JAB Jabber Event: This bit ...
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HUB MANAGEMENT SUPPORT Collision Bit Timer The Collision Timer counts, in bit times, the time between the start of repetition of the packet and the detection of the packet's first collision. When a collision occurs, the Colli- sion counter ...
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Port Block Functions The RIC2A has 13 port logic blocks (one for each network connection). In addition to the packet repetition operations already described, the port block performs two other func- tions: 1. the physical connection to the network ...
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... Filters like this are often packaged within magnetics mod- ules. These modules are currently available from Halo, Bel- fuse, Pulse, and Valor magnetics suppliers. This is a point for reference only. National Semiconductor does not qualify, recommend or claim conformance with any such device. Peak Differential Output Voltage (V ...
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Port Block Functions (Continued) Note 1: 1:2 turn ratio on transmit and 1:1 turn ratio on receive sides. Note 2: Transmit common mode chokes may not be required. Note 3: Please consult individual vendors for pin outline. Typical 16 ...
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Port Block Functions (Continued) 1:1 RJ45 TRANSFORMER Figure 20. Sample Twisted Pair Receive Filter connecting the resistor to GND will decrease V degree of change is related to the resistor value. The REQ input can be used to adjust ...
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Port Block Functions (Continued) Figure 21. IEEE Segment Partition Algorithm 48 www.national.com ...
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Port Block Functions (Continued) 6.4 Local Ports and Expected Activity The RIC2A incorporates security options into the repeater. The configuration of the security features can be performed globally per port basis. Upon packet reception by the ...
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RIC2A Registers RIC2A Register Address Map The RIC2A's registers may be accessed by applying the required address to the five Register Address (RA(4:0)) input pins. Pin RA4 makes the selection between the upper and lower halves of the register ...
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RIC2A Registers (Continued) Table 8. RIC2A Register Address Map (Continued) 19H res 1AH res 1BH res 1CH res GSR 1DH 1EH res 1FH IFG Threshold Select Address PAGE (4) 11H Port 1 ECR-2 12H Port 2 ECR-2 13H Port ...
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RIC2A Registers (Continued) Table 8. RIC2A Register Address Map (Continued) Address PAGE (13) 11H SCAM Lo 18 12H CLMR Lo Loc 18 13H CLMR Hi Loc 18 14H SCAM Lo 19 15H CLMR Lo Loc 19 16H CLMR Hi ...
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RIC2A Registers (Continued) Register Array Bit Map Addresses 11H to 1FH Page (1) Address D7 D6 (Hex BDLNK PART 1E ER8 ER7 1F DLU res Register Array Bit Map Addresses 11H to 1FH Pages (2) and ...
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RIC2A Registers (Continued) Register Array Bit Map Addresses 11H to 1FH Page (6) Address D7 D6 (Hex) 11 ADV PTR2 12, 13 PCAMx_D7 PCAMx_D6 14 res EDA 15 ADV PTR2 16, 17 PCAMx_D7 PCAMx_D6 18 res EDA 19 ADV ...
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RIC2A Registers (Continued) Register Array Bit Map Addresses 11H to 1FH Page (9) Address D7 D6 (Hex) 11 PCAMx PCAMx _D7 _D6 12 res EDA 13 ADV PTR2 14, 15 PCAMx PCAMx _D7 _D6 16 ADV8 ADV7 17 ADV16 ...
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RIC2A Registers (Continued) RIC2A Status and Configuration Register (Address 00H) The lower portion of this register contains real time information concerning the operation of the RIC2A. The D7 bit repre- sent the chosen configuration of the transceiver interface employed. ...
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RIC2A Registers (Continued) Port Real Time Status Registers (Address 01H to 0DH DISPT SQL PTYPE1 Bit R/W Symbol D0 R/W GDLNK D1 R COL D2 R REC D3 R/W PART D(5,4) R PTYPE0 PTYPE1 D6 R/W SQL ...
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RIC2A Registers (Continued) RIC2A Configuration Register This register displays the state of a number of RIC2A configuration bits loaded during the Mode Load operation MINMAX DPART Bit R/W Symbol D0 R GSE D1 R TW2 D2 R ...
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RIC2A Registers (Continued) Real Time Interrupt Register (Address 0FH) The Real Time Interrupt register (RTI) contains information which may change on a packet by packet basis. Any remain- ing interrupts which have not been serviced before the following packet ...
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RIC2A Registers (Continued) Page Select Register ((All pages) Address 10H) The Page Select register performs two functions enables switches to be made between register pages provides status information regarding the Event Logging Interrupts ...
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RIC2A Registers (Continued) Upper Event Count Mask Register (Page 0H Address 13H) The bits in this register effect the Upper and Lower Port Event Count Registers (ECR) on Page (3) addresses 12H to 1FH, and Page (4) addresses 12H ...
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RIC2A Registers (Continued) Event Count and Interrupt Mask Register 2 (ECIMR-2) (Page 0H Address 15H) The bits in this register effect the Port Event Count Register 2, PECR-2 on Page 4, Addresses 11H to 1DH res ISAM ...
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RIC2A Registers (Continued) Interrupt and Management Configuration Register (Page 0H Address 16H) This register powers up with all bits set to one and must be initialized by a processor write cycle before any events will generate interrupts ...
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RIC2A Registers (Continued) Packet Compress Decode Register (Page 0H Address 18H) This register is used to determine the number of bytes in the data field of a packet which are transferred over the manage- ment bus when the packet ...
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RIC2A Registers (Continued) Inter Frame Gap Threshold Select Register (Page 0H Address 1FH) This register is used to configure the hub management interface to provide a certain minimum inter frame gap between packets transmitted over the management bus. The ...
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RIC2A Registers (Continued) Lower Event Information Register (Lower EIR) (Page 1H Address 1FH DLU resv Bit R/W Symbol D0 R ER9 D1 R ER10 D2 R ER11 D3 R ER12 D4 R ER13 D5 R resv D6 ...
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RIC2A Registers (Continued) Port Event Count Register 2 (PECR-2) (Page 4H Addresses 11H to 1DH) The Port Event Count Register 2 (PECR-2) shows the instantaneous value of the specified port bit counter. The counter increments when an ...
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RIC2A Registers (Continued) Port CAM Pointer Register (PCPR) (Pages 4H, 5H, 6H, 8H, 9H) This register indicates which bytes of the six ethernet address bytes has been stored in the CAM locations. When a byte has been loaded into ...
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RIC2A Registers (Continued) Shared CAM Validation Register 1 (SCVR 1) (Page 9H Address 16H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs. When a “1” is written in a specific ...
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RIC2A Registers (Continued) Shared CAM Validation Register 2 (SCVR 2) (Page 9H, Address 17H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs. When a “1” is written in a specific ...
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RIC2A Registers (Continued) Shared CAM Validation Register 3 (SCVR 3) (Page 9H, Address 18H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs. When a “1” is written in a specific ...
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RIC2A Registers (Continued) Shared CAM Validation Register 4 (SCVR 4) (Page 9H Address 19H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs. When a “1” is written in a specific ...
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RIC2A Registers (Continued) Shared CAM Register (Pages 9H, AH, BH, CH, DH, EH, FH) This register accesses the 48 bits of the shared CAM address. Six write/read cycles are required to load/read the entire 48 bit address ...
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RIC2A Registers (Continued) CAM Location Mask Register (CLMR) (Pages 9H, AH, BH, CH, DH, EH, FH) Each shared CAM has a CLMR, therefore there are 32 CLMRs. Any of the 32 CAMs can be shared among the ports. For ...
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Board Layout Recommendations There are numerous methods to layout PCB boards to achieve successful proper operation. Two options for the RIC2A layout are presented here. These NSC recommen- dations have not been empirically proven in the laboratory. Power and ...
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Figure 24. The RIC2A Ground Plane is Divided into 3 Regions to Minimize Noise Effects Figure 25. The RIC2A Metal Layer Configuration used to Sink Additional Current Figure 26. Configuration for Decoupling Capacitors across Power & Ground Pins 76 www.national.com ...
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DC and AC Specification Absolute Maximum Ratings Supply Voltage ( ) Input Voltage ( Output Voltage (V out ) Storage Temperature Range (T STG ) Power Dissipation for chip ( Lead ...
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DC and AC Specification AC Specifications Port Arbitration Timing Number Symbol T1 ackilackol ACKI low to ACKO low T2 ackihackoh ACKI high to ACKO high Note 1: Timing valid with no receive or collision activities. Note 2: In these ...
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DC and AC Specification Receive Timing-10Base-T Ports Receive activity propagation start up and end delays for 10BASE-T ports Number Symbol T3t rxaackol RX active to ACKO low T4t rxiackoh RX inactive to ACKO high T5t rxaactna RX active to ...
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DC and AC Specification Transmit Timing-10Base-T Ports Receive activity propagation start up and end delays for 10BASE-T ports Number Symbol T15t actnatxa ACTNd active to TX active ACKI Note: assumed high COLLISION TIMING - AUI PORT Collision activity propagation ...
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DC and AC Specification Receive Collision Timing Number Symbol T32a cdacolna CD active to COLN active (Note 1) T33a cdicolni CD inactive to COLN inactive T39 colnajs COLN active to start of jam T40 colnije COLN inactive to end ...
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DC and AC Specification Collision Timing-AUI Port Number Symbol T34 anyamin ANYXN active time T35 anyitxai ANYXN inactive all inactive T38 anyasj ANYXN active to start of jam Number Symbol T36 actnitxi ACTN inactive to TX ...
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DC and AC Specification Inter RIC Bus Output Timing Number Symbol T101 ircoh IRC output high time T102 ircol IRC output low time T103 ircoc IRC output cycle time T104 actndapkena ACTNd active to PKEN active T105 actndairea ACTNd ...
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DC and AC Specification Inter RIC Bus Input Timing Number Symbol T111 ircih IRC input high time T122 ircil IRC input low time T114 irdisirc IRD input setup to IRC T115 irdihirc IRD input hold from IRC T116 ircihirei ...
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DC and AC Specification Management Bus Timing Number Symbol T50 mrxch MRXC high time T51 mrxcl MRXC low time T52 mrxcd MRXC cycle time T53 actndamena ACTNd active to MEN active T54 actndamcrsa ACTNd active to MCRS active T55 ...
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DC and AC Specification MLOAD TIMING Number Symbol T61 mldats data setup T62 mldath data hold T63 mlabufa MLOAD active to BUFEN active T64 mlibufi MLOAD inactive to BUFEN inactive T65 mlw MLOAD width T65a clkinm CLKIN setup to ...
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DC and AC Specification CDEC TIMING Number Symbol T70 cdecpw CDEC pulse width T71 cdeccdec CDEC to CDEC width REGISTER READ TIMING Number Symbol T80 rdadrs Read address setup T81 rdadrh Read address hold T82 rdabufa Read active to ...
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DC and AC Specification REGISTER WRITE TIMING Number Symbol T90 Write address setup T91 wradrh Write address hold T92 wrabufa Write active to BUFEN active T93 wribufi Write inactive to BUFEN inactive T94 wradatv Write active to Data valid ...
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DC and AC Specification AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken AUI side of the transformer. Input Pulse Levels (TTL/CMOS) Input Rise ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Molded Plastic Quad Package, JEDEC Order Number DP83953VUL NS Package Number VUL160A 2. A critical component is any component of a life support ...