ICS1893AFT IDT, Integrated Device Technology Inc, ICS1893AFT Datasheet - Page 15

• Manufacturer Part Number: ICS1893AFT
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AFT; 800-1920-2; ICS1893AFT

3.2 ISC1893AF Shared Features
ICS1893AF, Rev. D 10/26/04
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In the software control configuration the 10/100, DPXSEL and ANSEL pins are outputs.
Pins LSTA (link status) and LOCK (rec. PLL locked) are not brought out.
Input pin TXER is removed and tied low inside the package. The TXER function is still available by using
the Extended Control Register Reg 16 Bit 2. Most applications tied the TXER pin to VSS.
The same silicon die is used in the ICS1893AF and ICS1893Y-10
The ICS1893AF offers the same.35 3.3V low power operation.
Parametric specifications and timing diagrams are the same as ICS1893Y-10.
Both the ICS1893Y-10 and the ICS1893AF incorporate Digital Signal Processing in their PMD Sub layer,
thereby allowing them to transmit and receive data with Unshielded Twisted Pair (UTP) Category 5
cables up to 150 meters in length. In addition, this ICS-patented technology enables the ICS1893Y-10
ICS1893AF to address the effects of Baseline Wander correction.
Both ICS1893AF and ICS1893Y-10 have improved 10Base-T Squelch operation.
The ICS1893AF uses the same twisted pair transmitter and receive circuits and therefore the same
recommended board layout techniques apply.
Both share improved transmit circuits resulting in a decrease in the magnitude of the 10Base-T harmonic
content generated during transmission (reference ISO/IEC 8802-3: 1993 Clause 8.3.1.3).
Both use digital PLL technology resulting in lower jitter and improved stability.
The MDIO Maintenance interface with the MDIO and MDC pins along with all internal registers are
preserved in the ICS1893AF. This enables software configuring for FD/HD, 10Base-T, 100Base-TX and
Auto-Negotiation to be configurable by the MDIO maintenance interface. Default setting is
Auto-Negotiation Enable. All register settings are the same as in the ICS1893AF datasheet.
The ICS1893AF preserves the dual-purpose LED/Phy Address control pins as in the ICS1893Y-10. The
captured address seeds the scrambler for lower EMI in for multiple Phy applications.
All Auto-Negotiation features are preserved in the ICS1893AF. The reset default mode is A_N enabled.
The A_N parallel detect feature is preserved for legacy interoperability.
Both support Management Frame (MF) Preamble Suppression.
Both support backward compatibility with the ICS1890 Management Registers.
– Hardwired for Node configuration (NOD/REP pin removed, tied internally to VSS). Node
– Hardwired for Software mode (HW/SW pin removed, tied internally to VDD).
– Hardwired for MII interface only. (MII/SI pin removed, tied internally to VSS). In this configuration the
– DPXEL pin is not brought out.
– ANSEL pin is not brought out.
– 10/100 pin is brought out to indicate 100M operation. Some applications use this output to drive an
– LSTA and LOCK provided redundant information already available with the P2LI pin. P2LI indicates
– Only the package type is different.
ICS1893AF Data Sheet - Release
configuration enables the 10M SQE test default setting and causes CRS to be asserted for either
transmit or receive activity in half duplex, or for just receive activity when in full duplex.
10baseT serial and 100baseTX 5 bit symbol interfaces are NOT supported. Applications requiring
these interfaces should use ICS1893Y-10.
LED indicating 100M operation.
the Link is valid.
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
15
Chapter 3 Typical ICS1893AF Applications
October, 2004