ICS1893AFT IDT, Integrated Device Technology Inc, ICS1893AFT Datasheet - Page 54

• Manufacturer Part Number: ICS1893AFT
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AFT; 800-1920-2; ICS1893AFT

7.6.2.7 Management Frame Turnaround
7.6.2.8 Management Frame Data
7.6.2.9 Serial Management Interface Idle State
ICS1893AF, Rev D 10/26/04
A valid management frame includes a turn-around field (TA), which is a 2-bit time space between the
REGAD field and the Data field. This time allows an ICS1893AF and an STA to avoid contentions during
read transactions. During an operation that is a:
•
•
A valid management frame includes a 16-bit Data field for exchanging the register contents between the
ICS1893AF and the STA. All Management Registers are 16 bits wide, matching the width of the Data field.
During a transaction that is a:
•
•
If the STA attempts to:
•
•
Note:
The MDIO signal is in an idle state during the time between STA transactions. When the Serial
Management Interface is in the idle state, the ICS1893AF disables (that is, tri-states) its MDIO pin, which
enters a high-impedance state. The ISO/IEC 8802-3 standard requires that an MDIO signal be idle for at
least one bit time between management transactions. However, the ICS1893AF does not have this
limitation and can support a continual bit stream on its MDIO signals.
Read, an ICS1893AF remains in the high-impedance state during the first bit time and subsequently
drives its MDIO pin to logic zero for the second bit time.
Write, an ICS1893AF waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin.
Read, (OP is 10b) the ICS1893AF obtains the contents of the register identified in the REGAD field and
returns this Data to the STA synchronously with its MDC signal.
Write, (OP is 01b) the ICS1893AF stores the value of the Data field in the register identified in the
REGAD field.
Read from a non-existent ICS1893AF register, the ICS1893AF returns logic one for all bits in the Data
field, FFFFh.
Write to a non-existent ICS1893AF register, the ICS1893AF isolates the Data field of the management
frame from every reaching the registers.
ICS1893AF Data Sheet - Release
The first Data bit transmitted and received is the most-significant bit of a Management Register, bit
X.15.
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
54
Chapter 7 Functional Blocks
October, 2004