ICS1893AFT IDT, Integrated Device Technology Inc, ICS1893AFT Datasheet - Page 91

• Manufacturer Part Number: ICS1893AFT
• Description: PHYCEIVER LOW PWR 3.3V 48-SSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: PHYceiver™r
• Type: PHY Transceiverr

Specifications of ICS1893AFT

• Protocol: MII
• Voltage - Supply: 3.14 V ~ 3.47 V
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Other names: 1893AFT; 800-1920-2; ICS1893AFT

8.12.8 Halt Symbol (bit 17.6)
8.12.9 Premature End (bit 17.5)
8.12.10 Auto-Negotiation Complete (bit 17.4)
8.12.11 100Base-TX Signal Detect (bit 17.3)
ICS1893AF, Rev. D 10/26/04
The Halt Symbol bit indicates to an STA the detection of a Halt Symbol in a 100Base data stream by the
ICS1893AF.
During reception of a valid packet, the ICS1893AF examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. In addition, it looks for special symbols such as the Halt
Symbol. If a Halt Symbol is encountered, the ICS1893AF indicates this condition to the MAC/repeater.
If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
Note:
The Premature End bit indicates to an STA the detection of two consecutive Idles in a 100Base data stream
by the ICS1893AF.
During reception of a valid packet, the ICS1893AF examines each symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. If two consecutive Idles are encountered, it indicates
this condition to the MAC/repeater by setting this bit.
If this bit is set to a logic:
•
•
This bit is a latching high bit. (For more information on latching high and latching low bits, see
8.1.4.1, “Latching High Bits”
Note:
The Auto-Negotiation Complete bit is used to indicate to an STA the completion of the Auto-Negotiation
process. When this bit is set to logic:
•
•
The 100Base-TX Signal Detect bit indicates either the presence or absence of a signal on the Twisted-Pair
Receive pins (TP_RXP and TP_RXN) in 100Base-TX mode. This bit is logic:
•
•
Zero, it indicates a Halt Symbol has not been detected since either the last read or reset of this register.
One, it indicates a Halt Symbol was detected in the packet since either the last read or reset of this
register.
Zero, it indicates a Premature End condition has not been detected since either the last read or reset of
this register.
One, it indicates a Premature End condition was detected in the packet since either the last read or reset
of this register.
Zero, it indicates that the auto-negotiation process is either not complete or is disabled by the Control
Register’s Auto-Negotiation Enable bit (bit 0.12)
One, it indicates that the ICS1893AF has completed the auto-negotiation process and that the contents
of Management Registers 4, 5, and 6 are valid.
Zero when no signal is detected on the Twisted-Pair Receive pins.
One when a signal is present on the Twisted-Pair Receive pins.
ICS1893AF Data Sheet - Release
This bit has no definition in 10Base-T mode.
This bit has no definition in 10Base-T mode.
and
and
Copyright © 2004, Integrated Circuit Systems, Inc.
Section 8.1.4.2, “Latching Low
Section 8.1.4.2, “Latching Low
All rights reserved.
91
Bits”.)
Bits”.)
Chapter 8 Management Register Set
October, 2004
Section
Section